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Freescale Semiconductor Technical Data
Document Number: DSP56362 Rev. 4, 08/2006
DSP56362
24-Bit Audio Digital Signal Processor
1
Overview
Contents
1 2 3 4 5 6 A B Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Signal/Connection Descriptions . . . . . . . . . 2-1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Design Considerations . . . . . . . . . . . . . . . . 5-1 Ordering Information . . . . . . . . . . . . . . . . . . 6-1 Power Consumption Benchmark . . . . . . . . A-1 IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Freescale Semiconductor, Inc. designed the DSP56362 to support digital audio applications requiring digital audio compression and decompression, sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56362 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale SymphonyTM DSP family, as shown in Figure 1-1. This design provides a two-fold performance increase over Freescale's popular Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V.
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2006. All rights reserved.
Overview
Data Sheet Conventions This data sheet uses the following conventions: OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage* VIL / VOL VIH / VOH VIH / VOH VIL / VOL
Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
2
16
12
5
Program RAM/ Y Data X Data Instruction RAM RAM Cache 5632 x 24 5632 x 3072 x 24 Memory ROM Program ROM 24 Expansion 30K x 24 6144 x ROM Area Bootstrap ROM 24 6144 x 24 192 x 24
Triple Timer
DAX (SPDIF)
Host Interface
ESAI
SHI
PIO_EB
PM_EB
XM_EB
Address Generation Unit Six Channel DMA Unit
YAB XAB PAB DAB 24-Bit
YM_EB
Peripheral Expansion Area
18 External Address Bus Address Switch DRAM/SRAM Bus 11 Interface & I - Cache Control Control External Data Bus Switch 24 Data
DSP56300 Core DDB YDB XDB PDB GDB
Internal Data Bus Switch EXTAL Clock Generator PLL CLKOUT RESET PINIT/NMI MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD
Program Interrupt Controller
Program Decode Controller
Power Mngmnt. Data ALU Program 24 24 + 56 AE 56-bit MAC JTAG Address Two 56-bit Accumulators Generator OnCETM 56-bit Barrel Shifter
6
AA0456G
Figure 1-1 DSP56362 Block Diagram
DSP56362 Technical Data, Rev. 4 1-2 Freescale Semiconductor
Overview
1.1
*
Features
Multimode, multichannel decoder software functionality -- Dolby Digital and Pro Logic -- MPEG2 5.1 -- DTS -- Bass management Digital audio post-processing capabilities -- 3D Virtual surround sound -- Lucasfilm THX5.1 -- Soundfield processing -- Equalization Digital Signal Processing Core -- 100 MIPS with a 100 MHz clock at 3.3 V +/- 5% -- Object code compatible with the DSP56000 core -- Highly parallel instruction set -- Data arithmetic logic unit (ALU) - Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC) - 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing) - Conditional ALU instructions - 24-bit or 16-bit arithmetic support under software control -- Program control unit (PCU) - Position independent code (PIC) support - Addressing modes optimized for DSP applications (including immediate offsets) - On-chip instruction cache controller - On-chip memory-expandable hardware stack - Nested hardware DO loops - Fast auto-return interrupts -- Direct memory access (DMA) - Six DMA channels supporting internal and external accesses - One-, two-, and three- dimensional transfers (including circular buffering) - End-of-block-transfer interrupts - Triggering from interrupt lines and all peripherals -- Phase-locked loop (PLL) - Software programmable PLL-based frequency synthesizer for the core clock - Allows change of low-power divide factor (DF) without loss of lock - Output clock with skew elimination -- Hardware debugging support
DSP56362 Technical Data, Rev. 4
*
*
Freescale Semiconductor
1-3
Overview
*
- On-Chip Emulation (OnCE`) module - Joint Action Test Group (JTAG) test access port (TAP) - Address trace mode reflects internal program RAM accesses at the external port On-Chip Memories -- Modified Harvard architecture allows simultaneous access to program and data memories -- 30720 x 24-bit on-chip program ROM1 (disabled in 16-bit compatibility mode) -- 6144 x 24-bit on-chip X-data ROM1 -- 6144 x 24-bit on-chip Y-data ROM1 -- Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable
Instruction Cache Disabled Enabled Disabled Enabled Switch Mode Disabled Disabled Enabled Enabled Program RAM Size 3072 x 24-bit 2048 x 24-bit 5120 x 24-bit 4096 x 24-bit Instruction Cache Size 0 1024 x 24-bit 0 1024 x 24-bit X Data RAM Size Y Data RAM Size 5632 x 24-bit 5632 x 24-bit 5632 x 24-bit 5632 x 24-bit 5632 x 24-bit 5632 x 24-bit 3584 x 24-bit 3584 x 24-bit
.
*
*
-- 192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode) Off-Chip Memory Expansion -- Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using SRAM. -- Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using DRAM. -- External memory expansion port( twenty-four data pins for high speed external memory access allowing for a large number of external accesses per sample) -- Chip select logic for glueless interface to SRAMs -- On-chip DRAM controller for glueless interface to DRAMs Peripheral and Support Circuits -- Enhanced serial audio interface (ESAI) includes: - Six serial data lines, 4 selectable as receive or transmit and 2 transmit only. - Master or slave capability - I2S, Sony, AC97, and other audio protocol implementations -- Serial host interface (SHI) features: - SPI protocol with multi-master capability - I2C protocol with single-master capability - Ten-word receive FIFO - Support for 8-, 16-, and 24-bit words. -- Byte-wide parallel host interface (HDI08) with DMA support -- DAX features one serial transmitter capable of supporting S/PDIF, IEC958, IEC1937, CP-340, and AES/EBU digital audio formats; alternate configuration supports up to two GPIO lines
1. These ROMs may be factory programmed with data or programs provided by the application developer. DSP56362 Technical Data, Rev. 4 1-4 Freescale Semiconductor
Overview
*
-- Triple timer module with single external interface or GPIO line -- On-chip peripheral registers are memory mapped in data memory space Reduced Power Dissipation -- Very low-power (3.3 V) CMOS design -- Wait and stop low-power standby modes -- Fully-static logic, operation frequency down to 0 Hz (dc) -- Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent)
1.2
*
Package
144-pin plastic thin quad flat pack (LQFP) surface-mount package
1.3
Documentation
Table 1-1 lists the documents that provide a complete description of the DSP56362 and are required to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information).
Table 1-1 DSP56362 Documentation
Document Name DSP56300 Family Manual DSP56362 User's Manual DSP56362 Product Brief DSP56362 Data Sheet (this document) Description Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set Detailed description of memory, peripherals, and interfaces Brief description of the chip Electrical and timing specifications; pin and package descriptions Order Number DSP56300FM DSP56362UM DSP56362P DSP56362
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 1-5
Overview
NOTES
DSP56362 Technical Data, Rev. 4 1-6 Freescale Semiconductor
2
2.1
Signal/Connection Descriptions
Signal Groupings
The input and output signals of the DSP56362 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure 2-1. The DSP56362 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs.
Table 2-1 DSP56362 Functional Signal Groupings
Functional Group Power (VCC) Ground (GND) Clock and PLL Address bus Data bus Bus control Interrupt and mode control HDI08 SHI ESAI Digital audio transmitter (DAX) Timer JTAG/OnCE Port
1 2
Number of Signals 20 19 4 18 Port A
1
Detailed Description
Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14
24 11 5
Port B2
16 5
Port C3 Port D4
12 2 1 6
Port A is the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals. 3 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. 4 Port D signals are the GPIO port signals which are multiplexed with the DAX signals.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-1
Signal Groupings
DSP56362
VCCP VCCQH VCCQL VCCA VCCD VCCC VCCH VCCS
GNDP GNDP1
3 4 3 4 2 2
Power Inputs: PLL External I/O Internal Logic Address Bus Data Bus Bus Control HDI08 SHI/ESAI/DAX/Timer Grounds: PLL PLL Internal Logic Address Bus Data Bus Bus Control HDI08 SHI/ESAI/DAX/Timer
8
Host Interface (HDI08) Port1
GNDQ GNDA GNDD GNDC GNDH GNDS EXTAL CLKOUT PCAP PINIT/NMI
4 4 4 2 2
Non-Multiplexe d Bus H0-H7 HA0 HA1 HA2 HCS/HCS Single DS HRW HDS/HDS Single HR HOREQ/HOREQ HACK/HACK SPI Mode MOSI SS MISO SCK HREQ
Multiplexed Bus HAD0-HAD7 HAS/HAS HA8 HA9 HA10 Double DS HRD/HRD HWR/HWR Double HR HTRQ/HTRQ HRRQ/HRRQ
Port B GPIO PB0-PB7 PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15
Serial Host Interface (SHI)
I2C Mode HA0 HA2 SDA SCL HREQ Port C GPIO PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 Port D GPIO PD0 PD1 Timer GPIO TIO0
Clock and
PLL SCKR FSR HCKR SCKT FST HCKT SDO5/SDI0 SDO4/SDI1 SDO3/SDI2 SDO2/SDI3 SDO1 SDO0
Port A
A0-A17 D0-D23 AA0-AA3/ RAS0-RAS3 CAS RD WR TA BR BG BB MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET Notes: 1.
18 24
External Address Bus External Data Bus External Bus Control
Enhanced Serial Audio Interface (ESAI)2
4
Digital Audio Transmitter (DAX)2 Timer 02 Interrupt/ Mode Control
ACI ADO TIO0
2.
TCK TDI TDO JTAG/OnC TMS E Port TRST AA0601 DE The HDI08 port supports a nonmultiplexed or a multiplexed bus, single or double data strobe (DS), and single or double host request (HR) configurations. Since each of these modes is configured independently, any combination of these modes is possible. These HDI08 signals can also be configured alternately as GPIO signals (PB0-PB15). Signals with dual designations (e.g., HAS/HAS) have configurable polarity. The ESAI signals are multiplexed with the port C GPIO signals (PC0-PC11). The DAX signals are multiplexed with the Port D GPIO signals (PD0-PD1). The timer 0 signal can be configured alternately as the timer GPIO signal (TIO0).
Figure 2-1 Signals Identified by Functional Group
DSP56362 Technical Data, Rev. 4 2-2 Freescale Semiconductor
Power
2.2
Power
Table 2-2 Power Inputs
Power Name VCCP Description PLL Power--VCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP input. Quiet Core (Low) Power--VCCQL is an isolated power for the core processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCQ inputs. Quiet External (High) Power--VCCQH is a quiet power source for I/O lines. This input must be tied externally to all other chip power inputs. The user must provide adequate decoupling capacitors. There are three VCCQH inputs. Address Bus Power--VCCA is an isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are three VCCA inputs. Data Bus Power--VCCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCD inputs. Bus Control Power--VCCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCC inputs. Host Power--VCCH is an isolated power for the HDI08 I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCH input. SHI, ESAI, DAX, and Timer Power--VCCS is an isolated power for the SHI, ESAI, DAX, and Timer I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCS inputs.
VCCQL (4)
VCCQH (3)
VCCA (3)
VCCD (4)
VCCC (2)
VCCH
VCCS (2)
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-3
Ground
2.3
Ground
Table 2-3 Grounds
Description PLL Ground--GNDP is a ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip package. There is one GNDP connection. PLL Ground 1--GNDP1 is a ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. There is one GNDP1 connection. Quiet Ground--GNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDQ connections. Address Bus Ground--GNDA is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. Data Bus Ground--GNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDD connections. Bus Control Ground--GNDC is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDC connections. Host Ground--GNDH is an isolated ground for the HDI08 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDH connection. SHI, ESAI, DAX, and Timer Ground--GNDS is an isolated ground for the SHI, ESAI, DAX, and Timer I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDS connections.
Ground Name GNDP
GNDP1
GNDQ (4)
GNDA (4)
GNDD (4)
GNDC (2)
GNDH
GNDS (2)
2.4
Clock and PLL
Table 2-4 Clock and PLL Signals
Type Input State during Reset Input Signal Description External Clock Input--An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. This input cannot tolerate 5V.
Signal Name EXTAL
CLKOUT
Output
Chip-Driven
Clock Output--CLKOUT provides an output clock synchronized to the internal core clock phase. If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. CLKOUT is not functional at frequencies of 100 MHz and above.
DSP56362 Technical Data, Rev. 4 2-4 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 2-4 Clock and PLL Signals (continued)
Signal Name PCAP Type Input State during Reset Input Signal Description PLL Capacitor--PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating. PINIT/NMI Input Input PLL Initial/Non maskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET deassertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered non maskable interrupt (NMI) request internally synchronized to CLKOUT. PINIT/NMI cannot tolerate 5 V.
2.5
External Memory Expansion Port (Port A)
When the DSP56362 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port A signals: A0-A17, D0-D23, AA0/RAS0-AA3/RAS3, RD, WR, BB, CAS.
2.5.1
External Address Bus
Table 2-5 External Address Bus Signals
Type Output State during Reset Tri-Stated Signal Description Address Bus--When the DSP is the bus master, A0-A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0-A17 do not change state when external memory spaces are not being accessed.
Signal Name A0-A17
2.5.2
External Data Bus
Table 2-6 External Data Bus Signals
Type Input/Output State during Reset Tri-Stated Signal Description Data Bus--When the DSP is the bus master, D0-D23 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0-D23 are tri-stated.
Signal Name D0-D23
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-5
External Memory Expansion Port (Port A)
2.5.3
External Bus Control
Table 2-7 External Bus Control Signals
Type Output State during Reset Tri-Stated Signal Description Address Attribute or Row Address Strobe--When defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are can be tri-stated outputs with programmable polarity. Column Address Strobe--When the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the bus mastership enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated. Read Enable--When the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0-D23). Otherwise, RD is tri-stated. Write Enable--When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0-D23). Otherwise, the signals are tri-stated. Transfer Acknowledge--If the DSP56362 is the bus master and there is no external bus activity, or the DSP56362 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the bus control register (BCR), whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion, otherwise improper operation may result. TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the operating mode register (OMR). TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result.
Signal Name AA0-AA3/RA S0-RAS3
CAS
Output
Tri-Stated
RD
Output
Tri-Stated
WR
Output
Tri-Stated
TA
Input
Ignored Input
DSP56362 Technical Data, Rev. 4 2-6 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 2-7 External Bus Control Signals (continued)
Signal Name BR Type Output State during Reset Output (deasserted) Signal Description Bus Request--BR is an active-low output, never tri-stated. BR is asserted when the DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56362 is a bus master or a bus slave. Bus "parking" allows BR to be deasserted even though the DSP56362 is the bus master. (See the description of bus "parking" in the BB signal description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. Bus Grant--BG is an active-low input. BG is asserted by an external bus arbitration circuit when the DSP56362 becomes the next bus master. When BG is asserted, the DSP56362 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. The default mode of operation of this signal requires a setup and hold time referred to CLKOUT. But CLKOUT operation is not guaranteed from 100MHz and up, so the asynchronous bus arbitration must be used for clock frequencies 100MHz and above. The asynchronous bus arbitration is enabled by setting the ABE bit in the OMR register. BB Input/ Output Input Bus Busy--BB is a bidirectional active-low input/output. BB indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. This is called "bus parking" and allows the current bus master to reuse the bus without rearbitration until another device requires the bus. The deassertion of BB is done by an "active pull-up" method (i.e., BB is driven high and then released and held high by an external pull-up resistor). The default mode of operation of this signal requires a setup and hold time referred to CLKOUT. But CLKOUT operation is not guaranteed from 100MHz and up, so the asynchronous bus arbitration must be used for clock frequencies 100MHz and above. The asynchronous bus arbitration is enabled by setting the ABE bit in the OMR register. BB requires an external pull-up resistor.
BG
Input
Ignored Input
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-7
Interrupt and Mode Control
2.6
Interrupt and Mode Control
The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.
Table 2-8 Interrupt and Mode Control
Signal Name MODA/IRQA Type Input State during Reset Input Signal Description Mode Select A/External Interrupt Request A--MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. If IRQA is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQA to exit the wait state. If the processor is in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will exit the stop state. This input is 5 V tolerant. MODB/IRQB Input Input Mode Select B/External Interrupt Request B--MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQB is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQB to exit the wait state. This input is 5 V tolerant. MODC/IRQC Input Input Mode Select C/External Interrupt Request C--MODC/IRQC is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQC is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQC to exit the wait state. This input is 5 V tolerant.
DSP56362 Technical Data, Rev. 4 2-8 Freescale Semiconductor
Host Interface (HDI08)
Table 2-8 Interrupt and Mode Control (continued)
Signal Name MODD/IRQD Type Input State during Reset Input Signal Description Mode Select D/External Interrupt Request D--MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQD is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQD to exit the wait state. This input is 5 V tolerant. RESET Input Input Reset--RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. If RESET is deasserted synchronous to CLKOUT, exact start-up timing is guaranteed, allowing multiple processors to start synchronously and operate together in "lock-step." When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This input is 5 V tolerant.
2.7
Host Interface (HDI08)
The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.
2.7.1
Host Port Configuration
Signal functions associated with the HDI08 vary according to the interface operating mode as determined by the HDI08 port control register (HPCR). See 6.5.6 Host Port Control Register (HPCR) on page Section 6-13 for detailed descriptions of this register and (See Host Interface (HDI08) on page Section 6-1.) for descriptions of the other HDI08 configuration registers.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-9
Host Interface (HDI08)
Table 2-9 Host Interface
Signal Name H0-H7 Type Input/Output State during Reset Signal Description
GPIO Disconnected Host Data--When the HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, these signals are lines 0-7 of the bidirectional, tri-state data bus. Host Address--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 0-7 of the address/data bidirectional, multiplexed, tri-state bus. Port B 0-7--When the HDI08 is configured as GPIO, these signals are individually programmable as input, output, or internally disconnected. The default state after reset for these signals is GPIO disconnected. This input is 5 V tolerant.
HAD0-HAD7
Input/Output
PB0-PB7
Input, Output, or Disconnected
HA0
Input
GPIO Disconnected Host Address Input 0--When the HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address Strobe--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable, but is configured active-low (HAS) following reset. Port B 8--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
HAS/HAS
Input
PB8
Input, output, or disconnected
HA1
Input
GPIO Disconnected Host Address Input 1--When the HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus. Host Address 8--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus. Port B 9--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
HA8
Input
PB9
Input, Output, or Disconnected
DSP56362 Technical Data, Rev. 4 2-10 Freescale Semiconductor
Host Interface (HDI08)
Table 2-9 Host Interface (continued)
Signal Name HA2 Type Input State during Reset Signal Description
GPIO Disconnected Host Address Input 2--When the HDI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. Host Address 9--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus. Port B 10--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
HA9
Input
PB10
Input, Output, or Disconnected
HRW
Input
GPIO Disconnected Host Read/Write--When HDI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the Host Read/Write (HRW) input. Host Read Data--When HDI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host read data strobe (HRD) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HRD) after reset. Port B 11--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
HRD/HRD
Input
PB11
Input, Output, or Disconnected
HDS/HDS
Input
GPIO Disconnected Host Data Strobe--When HDI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HDS) following reset. Host Write Data--When HDI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HWR) following reset. Port B 12--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
HWR/HWR
Input
PB12
Input, Output, or Disconnected
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-11
Host Interface (HDI08)
Table 2-9 Host Interface (continued)
Signal Name HCS Type Input State during Reset Signal Description
GPIO Disconnected Host Chip Select--When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset. Host Address 10--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus.
HA10
Input
Port B 13--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
PB13
Input, Output, or Disconnected
DSP56362 Technical Data, Rev. 4 2-12 Freescale Semiconductor
Host Interface (HDI08)
Table 2-9 Host Interface (continued)
Signal Name HOREQ/HORE Type Output State during Reset Signal Description
GPIO Disconnected Host Request--When HDI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host request (HOREQ) output. The polarity of the host request is programmable, but is configured as active-low (HOREQ) following reset. The host request may be programmed as a driven or open-drain output. Transmit Host Request--When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable, but is configured as active-low (HTRQ) following reset. The host request may be programmed as a driven or open-drain output. Port B 14--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
HTRQ/HTRQ
Output
PB14
Input, Output, or Disconnected
HACK/HACK
Input
GPIO Disconnected Host Acknowledge--When HDI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK) after reset. Receive Host Request--When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable, but is configured as active-low (HRRQ) after reset. The host request may be programmed as a driven or open-drain output. Port B 15--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
HRRQ/HRRQ
Output
PB15
Input, Output, or Disconnected
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-13
Serial Host Interface
2.8
Serial Host Interface
Table 2-10 Serial Host Interface Signals
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
Signal Name SCK
Signal Type Input or Output
State during Reset Tri-Stated
Signal Description SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant.
SCL
Input or Output
MISO
Input or Output
Tri-Stated
SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant.
SDA
Input or Open-Drain Output
DSP56362 Technical Data, Rev. 4 2-14 Freescale Semiconductor
Serial Host Interface
Table 2-10 Serial Host Interface Signals (continued)
Signal Name MOSI Signal Type Input or Output State during Reset Tri-Stated Signal Description SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. SS Input Tri-Stated SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. HREQ Input or Output Tri-Stated Host Request--This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1-HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input is 5 V tolerant.
HA0
Input
HA2
Input
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-15
Enhanced Serial Audio Interface
2.9
Signal Name HCKR
Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals
Signal Type Input or Output State during Reset Signal Description
GPIO Disconnected High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port C 2--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
PC2
Input, Output, or Disconnected
HCKT
Input or Output
GPIO Disconnected High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port C 5--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
PC5
Input, Output, or Disconnected
FSR
Input or Output
GPIO Disconnected Frame Sync for Receiver--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.
PC1
Input, Output, or Disconnected
Port C 1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
DSP56362 Technical Data, Rev. 4 2-16 Freescale Semiconductor
Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
Signal Name FST Signal Type Input or Output State during Reset Signal Description
GPIO Disconnected Frame Sync for Transmitter--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port C 4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
PC4
Input, Output, or Disconnected
SCKR
Input or Output
GPIO Disconnected Receiver Serial Clock--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.
PC0
Input, Output, or Disconnected
Port C 0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
SCKT
Input or Output
GPIO Disconnected Transmitter Serial Clock--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port C 3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
PC3
Input, Output, or Disconnected
SDO5 SDI0 PC6
Output Input Input, Output, or Disconnected
GPIO Disconnected Serial Data Output 5--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C 6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-17
Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
Signal Name SDO4 SDI1 PC7 Signal Type Output Input Input, Output, or Disconnected State during Reset Signal Description
GPIO Disconnected Serial Data Output 4--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C 7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
SDO3 SDI2 PC8
Output Input Input, Output, or Disconnected
GPIO Disconnected Serial Data Output 3--When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. Port C 8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
SDO2 SDI3 PC9
Output Input Input, Output, or Disconnected
GPIO Disconnected Serial Data Output 2--When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register. Serial Data Input 3--When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. Port C 9--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
SDO1 PC10
Output Input, Output, or Disconnected
GPIO Disconnected Serial Data Output 1--SDO1 is used to transmit data from the TX1 serial transmit shift register. Port C 10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
SDO0 PC11
Output Input, Output, or Disconnected
GPIO Disconnected Serial Data Output 0--SDO0 is used to transmit data from the TX0 serial transmit shift register. Port C 11--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
DSP56362 Technical Data, Rev. 4 2-18 Freescale Semiconductor
Digital Audio Interface (DAX)
2.10
Signal Name ACI
Digital Audio Interface (DAX)
Table 2-12 Digital Audio Interface (DAX) Signals
Type Input State During Reset Disconnected Signal Description Audio Clock Input--This is the DAX clock input. When programmed to use an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 x Fs, 384 x Fs or 512 x Fs, respectively). Port D 0--When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
PD0
Input, Output, or Disconnected
ADO
Output
Disconnected
Digital Audio Data Output--This signal is an audio and non-audio output in the form of AES/EBU, CP340 and IEC958 data in a biphase mark format. Port D 1--When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
PD1
Input, Output, or Disconnected
2.11
Signal Name TIO0
Timer
Table 2-13 Timer Signal
Type Input or Output State During Reset Input Signal Description Timer 0 Schmitt-Trigger Input/Output--When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected it to Vcc through a pull-up resistor in order to ensure a stable logic level at the input. This input is 5 V tolerant.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-19
JTAG/OnCE Interface
2.12
Signal Name TCK
JTAG/OnCE Interface
Table 2-14 JTAG/OnCETM Interface
Type Input State During Reset Input Signal Description Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. This input is 5 V tolerant.
TDI
Input
Input
Test Data Input--TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant.
TDO
Output
Tri-Stated
Test Data Output--TDO is a test data serial output signal used for test instructions and data. TDO can be tri-stated and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode Select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant.
TMS
Input
Input
TRST
Input
Input
Test Reset--TRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. The use of TRST is not recommended for new designs. It is recommended to leave TRST disconnected. This input is 5 V tolerant.
DE
Input/Output
Input
Debug Event--DE is an open-drain, bidirectional, active-low signal providing, as an input, a means of entering the debug mode of operation from an external command controller, and, as an output, a means of acknowledging that the chip has entered the debug mode. This signal, when asserted as an input, causes the DSP56300 core to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the debug serial input line. This signal is asserted as an output for three clock cycles when the chip enters the debug mode as a result of a debug request or as a result of meeting a breakpoint condition. The DE has an internal pull-up resistor. This is not a standard part of the JTAG TAP controller. The signal connects directly to the OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered the debug mode. All other interface with the OnCE module must occur through the JTAG port. The use of DE is not recommended for new designs. It is recommended to leave DE disconnected. This input is not 5 V tolerant.
DSP56362 Technical Data, Rev. 4 2-20 Freescale Semiconductor
3
3.1
Specifications
Introduction
The DSP56362 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56362 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed. Finalized specifications will be published after full characterization and device qualifications are complete.
3.2
Maximum Ratings
CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 k. NOTE In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
Table 3-1 Maximum Ratings
Rating1 Symbol VCC VIN VIN5 I GND Value1, 2 Unit V V V mA
Supply Voltage All input voltages excluding "5 V tolerant" inputs3 All "5 V tolerant" input voltages3 Current drain per pin excluding VCC and GND
-0.3 to +4.0 -0.3 to VCC + 0.3
GND -0.3 to VCC + 3.95 10
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-1
Thermal Characteristics
Table 3-1 Maximum Ratings (continued)
Rating1 Operating temperature range Storage temperature
1 2
Symbol TJ TSTG
Value1, 2
Unit C C
-40 to +105 -55 to +125
GND = 0 V, VCC = 3.3 V .16 V, TJ = 0C to +100C, CL = 50 pF Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3 CAUTION: All "5 V Tolerant" input voltages must not be more than 3.95 V greater than the supply voltage; this restriction applies to "power on", as well as during normal operation. In any case, the input voltages cannot be more than 5.75 V. "5 V Tolerant" inputs are inputs that tolerate 5 V.
3.3
Thermal Characteristics
Table 3-2 Thermal Characteristics
Characteristic Symbol RJA or JA RJC or JC JT LQFP Value 45.3 10.1 5.5 Unit C/W C/W C/W
Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2
Thermal characterization parameter
1
Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111. Measurements were done with parts mounted on thermal test boards conforming to specification EIA/JESD51-3. 2 Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature.
3.4
DC Electrical Characteristics
Table 3-3 DC Electrical Characteristics1
Characteristics Symbol VCC Min 3.14 Typ 3.3 Max 3.46 Unit V V VIH VIHP 2.0 2.0 1.5 VIHX 0.8 x VCC -- -- -- VCC VCC + 3.95 VCC + 3.95 VCC V VIL VILP VILX -0.3 -0.3 -0.3 -0.3 -- -- -- 0.8 0.8 0.3 x VCC 0.2 x VCC
Supply voltage Input high voltage * D(0:23), BG, BB, TA, DE, and PINIT/NMI * MOD2/IRQ2, RESET, and TCK/TDI/TMS/ TRST/ESAI/Timer/HDI08/ SHI(SPI mode) pins
* SHI(I2C mode) pins * EXTAL3 Input low voltage * D(0:23), BG, BB, TA, MOD2/IRQ2, RESET, PINIT/NMI * All JTAG/ESAI/Timer/HDI08/ SHI(SPI mode) pins * SHI(I2C mode) pins * EXTAL
3
DSP56362 Technical Data, Rev. 4 3-2 Freescale Semiconductor
AC Electrical Characteristics
Table 3-3 DC Electrical Characteristics1 (continued)
Characteristics Input leakage current High impedance (off-state) input current (@ 2.4 V / 0.4 V) Output high voltage * TTL (IOH = -0.4 A) * CMOS (IOH = -10 A)4
4, 5
Symbol IIN ITSI VOH
Min -10 -10
Typ -- --
Max 10 10
Unit A A V
2.4 VCC - 0.01 VOL
4, 5
-- -- -- 0.4 0.01 A -- V
Output low voltage * TTL (IOL = 3.0 A, open-drain pins IOL = 6.7 A) * CMOS (IOL = 10 A)4
--
Internal supply current6 (Operating frequency 100MHz for current measurements) * In Normal mode * In Wait mode * In Stop mode
7
ICCI ICCW ICCS
-- -- -- --
127 7. 5 100 1 --
181 11 150 2.5 10 A pF
PLL supply current Input capacitance4
1 2 3
CIN
--
4 5 6
7
VCC = 3.3 V 5% V; TJ = 0C to +100C, CL = 50 pF Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins. Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 VCC and the maximum VILX should be no higher than 0.1 VCC. Periodically sampled and not 100% tested. This characteristic does not apply to PCAP. Section 5.3, "Power Consumption Considerations" provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.3 V at TJ = 100C. Maximum internal supply current is measured with VCC = 3.46 V at TJ = 100C. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float).
3.5
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56362 output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively. NOTE Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-3
Internal Clocks
3.6
Internal Clocks
Table 3-4 Internal Clocks, CLKOUT
Expression1, 2 Characteristics Symbol Min Typ (Ef x MF)/(PDF x DF) Max --
Internal operation frequency and CLKOUT with PLL enabled Internal operation frequency and CLKOUT with PLL disabled Internal clock and CLKOUT high period * With PLL disabled * With PLL enabled and MF 4 * With PLL enabled and MF > 4
f
--
f
--
Ef/2
--
TH -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF TL -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF TC -- ETC -- -- -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF -- ETC -- -- -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF
Internal clock and CLKOUT low period * With PLL disabled * With PLL enabled and MF 4 * With PLL enabled and MF > 4
Internal clock and CLKOUT cycle time with PLL enabled Internal clock and CLKOUT cycle time with PLL disabled Instruction cycle time
1
ETC x PDF x DF/MF 2 x ETC
TC
--
--
ICYC
--
TC
--
DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle 2 See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL.
DSP56362 Technical Data, Rev. 4 3-4 Freescale Semiconductor
EXTERNAL CLOCK OPERATION
3.7
EXTERNAL CLOCK OPERATION
The DSP56362 system clock is an externally supplied square wave voltage source connected to EXTAL (Figure 3-1)
VIHC EXTAL VILC ETH 2 4 5 CLKOUT With PLL Disabled 7 CLKOUT With PLL Enabled 6a Note: The midpoint is 0.5 (VIHC + VILC). 6b 7 AA0459 ETL 3 ETC 5 Midpoint
Figure 3-1 External Clock Timing Table 3-5 Clock Operation 100 and 120 MHz Values
100 MHz No. Characteristics Symbol Min 1 Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 3 ns maximum. 2 EXTAL input high1, 2 * With PLL disabled (46.7%-53.3% duty cycle)3 * With PLL enabled (42.5%-57.5% duty cycle) 3 EXTAL input low1, 2 * With PLL disabled (46.7%-53.3% duty cycle)3 * With PLL enabled (42.5%-57.5% duty cycle) 4 EXTAL cycle time2 * With PLL disabled * With PLL enabled 5 CLKOUT change from EXTAL fall with PLL disabled
3 3
120 MHz Min 0 Max 120.0
Max 100.0
Ef
0
ETH 4.67 ns 4.25 ns ETL 4.67 ns 4.25 ns ETC 10.00 ns 8.33 ns 8.33 ns -- 273.1 s 10.00 ns 273.1 s 4.3 ns 11.0 ns 157.0 s 4.67 ns 4.25 ns -- 1570.00 157.0 s 0.00 ns 0.00 ns 157.0 s
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-5
Phase Lock Loop (PLL) Characteristics
Table 3-5 Clock Operation (continued) 100 and 120 MHz Values
100 MHz No. Characteristics Symbol Min 6 CLKOUT rising edge from EXTAL rising edge with PLL enabled (MF = 1, PDF = 1, Ef > 15 MHz)4, 5 CLKOUT falling edge from EXTAL rising edge with PLL enabled (MF = 2 or 4, PDF = 1, Ef > 15 MHz)4, 5 CLKOUT falling edge from EXTAL falling edge with PLL enabled (MF 4, PDF 1, Ef / PDF > 15 MHz)4, 5 7 Instruction cycle time = ICYC = TC6 See Table ICYC 0.00 ns 0.00 ns 8.53 s 8.53 s 0.0 ns 0.0 ns 0.0 ns Max 1.8 ns 1.8 ns 1.8 ns Min Max 120 MHz
3-5 (46.7%-53.3% duty cycle)
* With PLL disabled * With PLL enabled
1 2 3
4 5 6
Measured at 50% of the input transition. The maximum value for PLL enabled is given for minimum VCO and maximum MF. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. Periodically sampled and not 100% tested. The skew is not guaranteed for any other MF value. The maximum value for PLL enabled is given for minimum VCO and maximum DF.
3.8
Phase Lock Loop (PLL) Characteristics
Table 3-6 PLL Characteristics
100 MHz Characteristics Min Max 200 MHz Unit
VCO frequency when PLL enabled (MF x Ef x 2/PDF) PLL external capacitor (PCAP pin to VCCP) (CPCAP)1 * @ MF 4 * @ MF > 4 Note:
1
30
(MF x 580) - 100 MF x 830
(MF x 780) - 140 MF x 1470
pF pF
CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (680 x MF) - 120, for MF 4, or 1100 x MF, for MF > 4
DSP56362 Technical Data, Rev. 4 3-6 Freescale Semiconductor
Reset, Stop, Mode Select, and Interrupt Timing
3.9
Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values1
100 MHz Min Max 26.0 120 MHz Unit Min Max 26.0 ns --
No 8 9
Characteristics Delay from RESET assertion to all pins at reset value3 Required RESET duration4 * Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled * Power on, internal oscillator * During STOP, XTAL disabled (PCTL Bit 16 = 0) * During STOP, XTAL enabled (PCTL Bit 16 = 1) * During normal operation
Expression2 --
50 x ETC 1000 x ETC 75000 x ETC 75000 x ETC 2.5 x TC 2.5 x TC
500.0 10.0 750 750 25.0 25.0
-- -- -- -- -- --
416.7 8.3 625 625 20.8 20.8
-- -- -- -- -- --
ns s s s ns ns
10 Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5 * Minimum * Maximum 11 Synchronous reset setup time from RESET deassertion to CLKOUT Transition 1 * Minimum * Maximum 12 Synchronous reset deasserted, delay time from the CLKOUT Transition 1 to the first external address output * Minimum * Maximum 13 Mode select setup time 14 Mode select hold time 15 Minimum edge-triggered interrupt request assertion width 16 Minimum edge-triggered interrupt request deassertion width 17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid * Caused by first interrupt instruction fetch * Caused by first interrupt instruction execution 18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution 4.25 x TC + 2.0 7.25 x TC + 2.0 10 x TC + 5.0 44.5 74.5 105.0 -- -- -- 37.4 62.4 88.3 ns ns ns 3.25 x TC + 2.0 20.25 TC + 7.5 33.5 -- 30.0 0.0 6.6 -- 207.5 -- -- -- 30.0 0.0 5.5 ns ns ns ns ns TC 5.9 -- -- 10.0 ns ns 3.25 x TC + 2.0 20.25 TC + 7.50 34.5 -- -- 211.5 29.1 176.2 ns ns
6.6
--
5.5
ns
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-7
Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values1 (continued)
No Characteristics Expression2 (3.75 + WS) x TC - 10.94 (3.25 + WS) x TC - 10.94 100 MHz Min 19 Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts6 20 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts6 21 Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts6 8 * DRAM for all WS * SRAM WS =1 * SRAM WS=2, 3 * SRAM WS 4 22 Synchronous interrupt setup time from IRQA, IRQB, IRQC, IRQD, NMI assertion to the CLKOUT Transition 2 23 Synchronous interrupt delay time from the CLKOUT Transition 2 to the first external address output valid caused by the first instruction fetch after coming out of Wait Processing state * Minimum * Maximum 24 Duration for IRQA assertion to recover from Stop state 25 Delay from IRQA assertion to fetch of first instruction (when exiting Stop)9, 3 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay) 26 Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)9, 3 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) PLC x ETC x PDF + (128K - PLC/2) x TC PLC x ETC x PDF + (20.5 0.5) x TC 5.5 x TC 13.6 12.3 55.0 -- -- -- 45.8 -- ms ms ns PLC x ETC x PDF + (128 K - PLC/2) x TC PLC x ETC x PDF + (23.75 0.5) x TC (8.25 0.5) x TC 1.3 232.5 ns 77.5 13.6 12.3 ms 87.5 -- -- 64.6 -- -- 72.9 ns ms 9.25 x TC + 1.0 24.75 x TC + 5.0 0.6 x TC - 0.1 93.5 -- 5.9 -- 252.5 -- 78.1 -- 4.9 -- 211.2 -- ns ns ns (WS + 3.5) x TC - 10.94 (WS + 3.5) x TC - 10.94 1.75 x TC - 4.0 2.75 x TC - 4.0 0.6 x TC - 0.1 -- -- -- --
5.9
120 MHz Unit Min -- Max Note 7 ns
Max Note7
--
--
Note 7
--
Note 7
Note 7 Note 7 Note 7 Note 7
-- -- -- -- 4.9
Note 7 Note 7 Note 7 Note 7 --
ns ns ns ns ns
DSP56362 Technical Data, Rev. 4 3-8 Freescale Semiconductor
Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values1 (continued)
No Characteristics Expression2 100 MHz Min 27 Interrupt Requests Rate * HI08, ESAI, SHI, Timer * DMA * IRQ, NMI (edge trigger) * IRQ, NMI (level trigger) 28 DMA Requests Rate * Data read from HI08, ESAI, SHI * Data write to HI08, ESAI, SHI * Timer * IRQ, NMI (edge trigger) 29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid
1 2 3 4
120 MHz Unit Min Max
Max
12TC 8TC 8TC 12TC
-- -- -- --
120.0 80.0 80.0 120.0
-- -- -- --
100.0 66.7 66.7 100.0
ns ns ns ns
6TC 7TC 2TC 3TC 4.25 x TC + 2.0
-- -- -- -- 44.0
60.0 70.0 20.0 30.0 --
-- -- -- -- 37.4
50.0 58.0 16.7 25.0 --
ns ns ns ns ns
5 6
7 8 9
VCC = 3.3 V 0.16 V; TJ = 0C to +100C, CL = 50 pF Use expression to compute maximum value. Periodically sampled and not 100% tested. For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. If PLL does not lose lock. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. These values depend on the number of wait states (WS) selected. WS = number of wait states (measured in clock cycles, number of TC. This timing depends on several settings: For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case. For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored). For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings. For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. PLC value for PLL disable is 0. The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100 MHz it is 4096/100 MHz = 40.96s). During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary as well.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-9
Reset, Stop, Mode Select, and Interrupt Timing VIH RESET
9 8 All Pins Reset Value
10
A0-A17
First Fetch AA0460
Figure 3-2 Reset Timing
CLKOUT
11 RESET 12
A0-A17 AA0461
Figure 3-3 Synchronous Reset Timing
DSP56362 Technical Data, Rev. 4 3-10 Freescale Semiconductor
Reset, Stop, Mode Select, and Interrupt Timing
A0-A17
First Interrupt Instruction Execution/Fetch
RD 20
WR 21
IRQA, IRQB, IRQC, IRQD, NMI
17
19
a) First Interrupt Instruction Execution
General Purpose I/O
18 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O AA0462
Figure 3-4 External Fast Interrupt Timing
IRQA, IRQB, IRQC, IRQD, NMI 15 IRQA, IRQB, IRQC, IRQD, NMI
16 AA0463
Figure 3-5 External Interrupt Timing (Negative Edge-Triggered)
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-11
Reset, Stop, Mode Select, and Interrupt Timing
CLKOUT
IRQA, IRQB, IRQC, IRQD, NMI
22
23 A0-A17 AA0464
Figure 3-6 Synchronous Interrupt from Wait State Timing
RESET 13 14 MODA, MODB, MODC, MODD, PINIT VIH VIL VIH VIL
VIH
IRQA, IRQB, IRQC, IRQD, NMI
AA0465
Figure 3-7 Operating Mode Select Timing
24 IRQA
25 A0-A17 First Instruction Fetch AA0466
Figure 3-8 Recovery from Stop State Using IRQA
DSP56362 Technical Data, Rev. 4 3-12 Freescale Semiconductor
Reset, Stop, Mode Select, and Interrupt Timing
26 IRQA
25 A0-A17 First IRQA Interrupt Instruction Fetch AA0467
Figure 3-9 Recovery from Stop State Using IRQA Interrupt Service
A0-A17
DMA Source Address
RD
WR 29 IRQA, IRQB, IRQC, IRQD, NMI First Interrupt Instruction Execution AA1104
Figure 3-10 External Memory Access (DMA Source) Timing
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-13
External Memory Expansion Port (Port A)
3.10
3.10.1
External Memory Expansion Port (Port A)
SRAM Timing
Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz1
100 MHz Min Max -- 120 MHz Unit Min 12.0 Max -- ns 16.0
No.
Characteristics
Symbol tRC, tWC
Expression2 (WS + 1) x TC - 4.0 [1 WS 3] (WS + 2) x TC - 4.0 [4 WS 7] (WS + 3) x TC - 4.0 [WS 8]
100 Address valid and AA assertion pulse width3
56.0
--
46.0
--
ns
106.0
--
87.0
--
ns
101 Address and AA valid to WR assertion
tAS
100 MHz: 0.25 x TC - 2.0 [WS = 1] 1.25 x TC - 2.0 [WS 4]
0.5
--
0.1
--
ns
10.5
--
8.4
--
ns
102 WR assertion pulse width
tWP
100 MHz: 1.5 x TC - 4.0 [WS = 1] All frequencies: WS x TC - 4.0 [2 WS 3] (WS - 0.5) x TC - 4.0 [WS 4]
11.0
--
8.5
--
ns
16.0
--
12.7
--
ns
31.0
---
25.2
--
103 WR deassertion to address not valid
tWR
100 MHz: 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] All frequencies: 1.25 x TC - 4.0 [4 WS 7] 2.25 x TC - 4.0 [WS 8]
0.5
--
0.1
--
ns
10.5
--
8.4
--
20.5
--
16.7
--
8.5
--
6.4
--
18.5
--
14.7
--
DSP56362 Technical Data, Rev. 4 3-14 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz1 (continued)
No. Characteristics Symbol tAA, tAC Expression2 100 MHz: (WS + 0.75) x TC - 7.0 [WS 1] 105 RD assertion to input data valid tOE 100 MHz: (WS + 0.25) x TC - 7.0 [WS 1] 106 RD deassertion to data not valid (data hold time) 107 Address valid to WR deassertion3 tOHZ tAW (WS + 0.75) x TC - 4.0 [WS 1] 108 Data valid to WR deassertion (data setup time) tDS (tDW) 100 MHz: (WS - 0.25) x TC - 3.0 [WS 1] 109 Data hold time from WR deassertion tDH 100 MHz: 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] 110 WR assertion to data active4 0.75 x TC - 3.7 [WS = 1] 0.25 x TC - 3.7 [2 WS 3] -0.25 x TC - 3.7 [WS 4] 111 WR deassertion to data high impedance4 0.25 x TC + 0.2 [1 WS 3] 1.25 x TC + 0.2 [4 WS 7] 2.25 x TC + 0.2 [WS 8] -- -- -- 18.9 -- -- -- 10.6 -- -- -- 2.3 ns -- -- 0.0 -- -- -- 0.0 -- -- -- 2.5 -- ns 20.5 -- 16.7 -- 10.5 -- 8.4 -- 0.5 -- 0.1 -- ns 4.5 -- 3.2 -- ns 0.0 -- 0.0 -- ns -- 5.5 -- 3.4 ns 100 MHz Min 104 Address and AA valid to input data valid -- Max 10.5 120 MHz Unit Min Max 7.6 ns
13.5
--
10.6
--
ns
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-15
External Memory Expansion Port (Port A)
Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz1 (continued)
No. Characteristics Symbol Expression2 1.25 x TC - 4.0 [1 WS 3] 2.25 x TC - 4.0 [4 WS 7] 3.25 x TC - 4.0 [WS 8] 113 RD deassertion time 100 MHz: 0.75 x TC - 4.0 [1 WS 3] 1.75 x TC - 4.0 [4 WS 7] 2.75 x TC - 4.0 [WS 8] 114 WR deassertion time 100 MHz: 0.5 x TC - 4.0 [WS = 1] TC - 2.0 [2 WS 3] 2.5 x TC - 4.0 [4 WS 7] 3.5 x TC - 4.0 [WS 8] 115 Address valid to RD assertion 100 MHz: 0.5 x TC - 4.0 116 RD assertion pulse width 100 MHz: (WS + 0.25) x TC -4.0 117 RD deassertion to address not valid 100 MHz: 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] 20.5 -- 16.7 -- 10.5 -- 8.4 -- 0.5 -- 0.1 -- ns 8.5 -- 6.4 -- ns 1.0 -- 0.2 -- ns 31.0 -- 25.2 -- 21.0 -- 16.8 -- 6.0 -- 6.3 -- 1.0 -- 0.2 -- ns 23.5 -- 18.9 -- 13.5 -- 10.6 -- 3.5 -- 2.2 -- ns -- -- 23.1 -- -- -- 14.7 -- 100 MHz Min 112 Previous RD deassertion to data active (write)4 -- Max -- 120 MHz Unit Min 6.4 Max -- ns
DSP56362 Technical Data, Rev. 4 3-16 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz1 (continued)
No. Characteristics Symbol Expression2 0.25 x TC + 2.0 100 MHz Min 118 TA setup before RD or WR deassertion5 119 TA hold after RD or WR deassertion
1 2
120 MHz Unit Min 4.1 0.0 Max -- -- ns ns
Max -- --
4.5 0
All timings for 100 MHz are measured from 0.5 Vcc to .05 Vcc WS is the number of wait states specified in the BCR. 3 Timings 100, 107 are guaranteed by design, not tested. 4 Timing 110, 111, and 112, are not specified for 100 MHz. 5 In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active.
100 A0-A17 AA0-AA3 113 RD 115 WR 104 119 TA D0-D23 Data In AA0468 118 105 106 116 117
Figure 3-11 SRAM Read Access
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-17
External Memory Expansion Port (Port A)
100 A0-A17 AA0-AA3 107 101 WR 114 RD 119 TA 108 110 112 D0-D23 Data Out AA0469 109 111 118 102 103
Figure 3-12 SRAM Write Access
3.10.2
DRAM Timing
The selection guides provided in Figure 3-13 and Figure 3-16 should be used for primary selection only. Final selection should be based on the timing provided in the following tables. As an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control factors such as capacitive and resistive load to improve overall system performance.
DSP56362 Technical Data, Rev. 4 3-18 Freescale Semiconductor
External Memory Expansion Port (Port A) DRAM Type (tRAC ns) Note: This figure should be used for primary selection. For exact and detailed timings see the following tables.
100
80
70
60
50 40 66 80 100 120
Chip Frequency (MHz)
1 Wait States 2 Wait States
3 Wait States 4 Wait States AA0472
Figure 3-13 DRAM Page Mode Wait States Selection Guide Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3
20 MHz4 No. Characteristics Symbol tPC Expression Min 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses. 132 CAS assertion to data valid (read) 133 Column address valid to data valid (read) 134 CAS deassertion to data not valid (read hold time) 135 Last CAS assertion to RAS deassertion 136 Previous CAS deassertion to RAS deassertion tCAC tAA tOFF tRSH tRHCP 0.75 x TC - 4.0 2 x TC - 4.0 2 x TC 1.25 x Tc TC - 7.5 1.5 x TC - 7.5 100.0 62.5 Max -- -- Min 66.7 41.7 Max -- -- ns 30 MHz4 Unit
-- -- 0.0
42.5 67.5 --
-- -- 0.0
25.8 42.5 --
ns ns ns
33.5 96.0
-- --
21.0 62.7
-- --
ns ns
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-19
External Memory Expansion Port (Port A)
Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (continued)
20 MHz4 No. Characteristics Symbol tCAS tCRP 1.75 x TC - 6.0 3.25 x TC - 6.0 4.25 x TC - 6.0 6.25 x TC - 6.0 tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA tGZ 0.75 x TC - 0.3 0.25 x TC 0.5 x TC - 4.0 0.5 x TC - 4.0 0.75 x TC - 4.0 2 x TC - 4.0 0.75 x TC - 3.8 0.25 x TC - 3.7 0.5 x TC - 4.2 1.5 x TC - 4.5 1.75 x TC - 4.3 1.75 x TC - 4.3 0.25 x TC - 4.0 0.75 x TC - 4.0 TC - 4.3 1.5 x TC - 4.0 TC - 7.5 81.5 156.5 206.5 306.5 21.0 21.0 33.5 96.0 33.7 8.8 20.8 70.5 83.2 83.2 8.5 33.5 45.7 71.0 -- 0.0 37.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 42.5 -- -- 12.5 52.3 102.2 135.5 202.1 12.7 12.7 21.0 62.7 21.2 4.6 12.5 45.5 54.0 54.0 4.3 21.0 29.0 46.0 -- 0.0 24.7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 25.8 -- -- 8.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Expression Min 137 CAS assertion pulse width 138 Last CAS deassertion to RAS deassertion5 * BRW[1:0] = 00 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 139 CAS deassertion pulse width 140 Column address valid to CAS assertion 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion 145 CAS assertion to WR deassertion 146 WR assertion pulse width 147 Last WR assertion to RAS deassertion 148 WR assertion to CAS deassertion 149 Data valid to CAS assertion (Write) 150 CAS assertion to data not valid (write) 151 WR assertion to CAS assertion 152 Last RD assertion to RAS deassertion 153 RD assertion to data valid 154 RD deassertion to data not valid 6 155 WR assertion to data active 156 WR deassertion to data high impedance
1 2 3 4 5 6
30 MHz4 Unit Min 21.0 Max -- ns ns
Max --
0.75 x TC - 4.0
33.5
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 2 x TC for read-after-read or write-after-write sequences). Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state. See Figure 3-13. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
DSP56362 Technical Data, Rev. 4 3-20 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4
80 MHz No. Characteristics Symbol Expression Min 131 Page mode cycle time for two consecutive accesses of the same direction5 Page mode cycle time for mixed (read and write) accesses.5 132 133 134 135 136 137 138 CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS deassertion6 * BRW[1:0] = 00 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 139 140 141 142 143 144 145 146 147 148 149 150 151 152 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tCAC tAA tOFF tRSH tRHCP tCAS tCRP 2.0 x TC - 6.0 3.5 x TC - 6.0 4.5 x TC - 6.0 6.5 x TC - 6.0 1.25 x TC - 4.0 TC - 4.0 1.75 x TC - 4.0 3 x TC - 4.0 1.25 x TC - 3.8 0.5 x TC - 3.7 1.5 x TC - 4.2 2.5 x TC - 4.5 2.75 x TC - 4.3 2.5 x TC - 4.3 0.25 x TC - 3.0 1.75 x TC - 4.0 TC - 4.3 2.5 x TC - 4.0 19.0 37.8 50.3 75.3 11.6 8.5 17.9 33.5 11.8 2.6 14.6 26.8 30.1 27.0 0.1 17.9 8.2 27.3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.75 x TC - 4.0 3.25 x TC - 4.0 1.5 x TC - 4.0 tPC 3 x TC 2.75 x Tc 1.5 x TC - 6.5 2.5 x TC - 6.5 37.5 34.4 -- -- 0.0 17.9 36.6 14.8 Max -- -- 12.3 24.8 -- -- -- -- ns ns ns ns ns ns ns ns Unit
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-21
External Memory Expansion Port (Port A)
Table 3-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4 (continued)
80 MHz No. Characteristics Symbol Expression Min 153 154 155 156
1 2 3 4 5 6 7
Unit Max 15.4 -- -- 3.1 ns ns ns ns
RD assertion to data valid RD deassertion to data not valid7 WR assertion to data active WR deassertion to data high impedance
tGA tGZ
1.75 x TC - 6.5
-- 0.0
0.75 x TC - 0.3 0.25 x TC
9.1 --
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56362. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 x TC for read-after-read or write-after-write sequences). There are not any fast enough DRAMs to fit to two wait states Page mode @ 100MHz. See Figure 3-13. BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
Table 3-11 DRAM Page Mode Timings, Three Wait States1, 2, 3, 4
100 MHz No. Characteristics Symbol Expression Min 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses. 132 CAS assertion to data valid (read) tCAC tPC 4 x TC 3.5 x Tc 100 MHz: 2 x TC - 7.0 133 Column address valid to data valid (read) tAA 100 MHz: 3 x TC - 7.0 134 CAS deassertion to data not valid (read hold time) 135 Last CAS assertion to RAS deassertion 136 Previous CAS deassertion to RAS deassertion 137 CAS assertion pulse width 138 Last CAS deassertion to RAS assertion5 * BRW[1:0] = 00 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 tOFF tRSH tRHCP tCAS tCRP 2.25 x TC - 6.0 3.75 x TC - 6.0 4.75 x TC - 6.0 6.75 x TC - 6.0 -- -- 41.5 61.5 -- -- -- -- 2.5 x TC - 4.0 4.5 x TC - 4.0 2 x TC - 4.0 0.0 21.0 41.0 16.0 -- -- -- -- ns ns ns ns ns -- 23.0 ns 40.0 35.0 -- Max -- -- 13.0 ns ns Unit
DSP56362 Technical Data, Rev. 4 3-22 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-11 DRAM Page Mode Timings, Three Wait States1, 2, 3, 4 (continued)
100 MHz No. Characteristics Symbol Expression Min 139 CAS deassertion pulse width 140 Column address valid to CAS assertion 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion tCP tASC tCAH tRAL tRCS 1.5 x TC - 4.0 TC - 4.0 2.5 x TC - 4.0 4 x TC - 4.0 100 MHz: 1.25 x TC - 4.0 144 CAS deassertion to WR assertion tRCH 100 MHz: 0.75 x TC - 4.0 145 CAS assertion to WR deassertion 146 WR assertion pulse width 147 Last WR assertion to RAS deassertion 148 WR assertion to CAS deassertion 149 Data valid to CAS assertion (write) 150 CAS assertion to data not valid (write) 151 WR assertion to CAS assertion 152 Last RD assertion to RAS deassertion 153 RD assertion to data valid tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA 2.25 x TC - 4.2 3.5 x TC - 4.5 3.75 x TC - 4.3 3.25 x TC - 4.3 0.5 x TC - 4.0 2.5 x TC - 4.0 1.25 x TC - 4.3 3.5 x TC - 4.0 100 MHz: 2.5 x TC - 7.0 154 RD deassertion to data not valid6 155 WR assertion to data active 156 WR deassertion to data high impedance
1 2 3 4 5 6
Unit Max -- -- -- -- ns ns ns ns ns
11.0 6.0 21.0 36.0 8.5
3.5
ns
18.3 30.5 33.2 28.2 1.0 21.0 8.2 31.0 --
-- -- -- -- -- -- -- -- 18.0
ns ns ns ns ns ns ns ns ns
tGZ 0.75 x TC - 0.3 0.25 x TC
0.0 7.2 --
-- -- 2.5
ns ns ns
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56362. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-23
External Memory Expansion Port (Port A)
Table 3-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz1, 2, 3, 4
100 MHz No. Characteristics Symbol Expression Min 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses. 132 CAS assertion to data valid (read) tCAC tPC 5 x TC 4.5 x TC 50.0 45.0 Max -- -- Min 41.7 37.5 Max ns 120 MHz Unit
100 MHz: 2.75 x TC - 7.0
--
20.5
--
15.9
ns
133
Column address valid to data valid (read)
tAA
100 MHz: 3.75 x TC - 7.0
--
30.5
--
24.2
ns
134 135 136 137 138
CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS assertion5
tOFF tRSH tRHCP tCAS tCRP 2.75 x TC - 6.0 4.25 x TC - 6.0 5.25 x TC - 6.0 7.25 x TC - 6.0 tCP tASC tCAH tRAL tRCS 2 x TC - 4.0 TC - 4.0 3.5 x TC - 4.0 5 x TC - 4.0 100 MHz: 1.25 x TC - 4.0 3.5 x TC - 4.0 6 x TC - 4.0 2.5 x TC - 4.0
0.0 31.0 56.0 21.0
-- -- -- --
0.0 25.2 46.0 16.8
-- -- -- --
ns ns ns ns ns
BRW[1:0] = 00 BRW[1:0] = 01 BRW[1:0] = 10 BRW[1:0] = 11
139 140 141 142 143 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion
-- -- 46.5 66.5 16.0 6.0 31.0 46.0 8.5
-- -- -- -- -- -- -- -- --
-- -- 37.7 54.4 12.7 4.3 25.2 37.7 6.4
-- -- -- -- -- -- -- -- -- ns ns ns ns ns
144
CAS deassertion to WR assertion
tRCH
100 MHz: 1.25 x TC - 4.0
8.5
--
6.4
--
ns
145 146 147 148
CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion
tWCH tWP tRWL tCWL
3.25 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 3.75 x TC - 4.3
28.3 40.5 43.2 33.2
-- -- -- --
22.9 33.0 35.3 26.9
-- -- -- --
ns ns ns ns
DSP56362 Technical Data, Rev. 4 3-24 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz1, 2, 3, 4 (continued)
100 MHz No. Characteristics Symbol Expression Min 149 150 151 152 153 Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid tDS tDH tWCS tROH tGA 0.5 x TC - 4.0 3.5 x TC - 4.0 1.25 x TC - 4.3 4.5 x TC - 4.0 100 MHz: 3.25 x TC - 7.0 154 155 156
1 2 3 4 5 6
120 MHz Unit Min 0.2 25.2 6.1 33.5 -- Max -- -- -- -- 20.1 ns ns ns ns ns
Max -- -- -- -- 25.5
1.0 31.0 8.2 41.0 --
RD deassertion to data not valid6 WR assertion to data active WR deassertion to data high impedance
tGZ 0.75 x TC - 0.3 0.25 x TC
0.0 7.2 --
-- -- 2.5
0.0 5.9 --
--
ns ns
2.1
ns
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56362. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-25
External Memory Expansion Port (Port A)
RAS 136 131 CAS 137 140 141 A0-A17 Row Add Column Address 151 145 Column Address 144 142 Last Column Address 143 147 139 138 135
WR 146 RD 155 150 149 D0-D23 Data Out Data Out Data Out AA0473 156 148
Figure 3-14 DRAM Page Mode Write Accesses
DSP56362 Technical Data, Rev. 4 3-26 Freescale Semiconductor
External Memory Expansion Port (Port A)
RAS 136 131 CAS 137 140 Row Add Column Address 143 WR 132 133 153 RD 134 154 D0-D23 Data In Data In Data In AA0474 152 139 141 Column Address 138 142 Last Column Address 135
A0-A17
Figure 3-15 DRAM Page Mode Read Accesses
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-27
External Memory Expansion Port (Port A) DRAM Type (tRAC ns)
Note: This figure should be use for primary selection. For exact and detailed timings see the following tables.
100
80
70
60
50 40 66 80 100 120 11 Wait States 15 Wait States
Chip Frequency (MHz)
4 Wait States 8 Wait States
AA0475
Figure 3-16 DRAM Out-of-Page Wait States Selection Guide Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2
20 MHz4 No. Characteristics3 Symbol Expression Min 157 158 159 160 161 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion tRC tRAC tCAC tAA tOFF 1.75 x TC - 4.0 3.25 x TC - 4.0 1.75 x TC - 4.0 5 x TC 2.75 x TC - 7.5 1.25 x TC - 7.5 1.5 x TC - 7.5 250.0 -- -- -- 0.0 Max -- 130.0 55.0 67.5 -- Min 166.7 -- -- -- 0.0 Max -- 84.2 34.2 42.5 -- ns ns ns ns ns 30 MHz4 Unit
162 163 164
tRP tRAS tRSH
83.5 158.5 83.5
-- -- --
54.3 104.3 54.3
-- -- --
ns ns ns
DSP56362 Technical Data, Rev. 4 3-28 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (continued)
20 MHz4 No. Characteristics
3
30 MHz4 Unit Min 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 4.3 54.3 104.3 62.7 46.2 21.3 4.6 45.8 95.8 145.5 154.0 137.4 71.0 54.3 104.3 95.7 12.7 37.7 Max -- -- 52.0 43.7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
Expression Min Max -- -- 77.0 64.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.75 x TC - 4.0 1.25 x TC - 4.0 1.5 x TC 2 1.25 x TC 2 2.25 x TC - 4.0 1.75 x TC - 4.0 1.75 x TC - 4.0 1.25 x TC - 4.0 0.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 2 x TC - 4.0 1.5 x TC - 3.8 0.75 x TC - 3.7 0.25 x TC - 3.7 1.5 x TC - 4.2 3 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 4.25 x TC - 4.3 2.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 3 x TC - 4.3 0.5 x TC - 4.0 1.25 x TC - 4.0
165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion RAS deassertion to WR assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh)
tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC
133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 8.5 83.5 158.5 96.0 71.2 33.8 8.8 70.8 145.8 220.5 233.2 208.2 108.5 83.5 158.5 145.7 21.0 58.5
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-29
External Memory Expansion Port (Port A)
Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (continued)
20 MHz4 No. Characteristics
3
30 MHz4 Unit Min 146.0 -- 0.0 24.7 -- Max -- 125.8 -- -- 8.3 ns ns ns ns ns
Symbol
Expression Min Max -- 192.5 -- -- 12.5 4.5 x TC - 4.0 4 x TC - 7.5
191 192 193 194 195
1 2
RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance
tROH tGA tGZ
221.0 -- 0.0
0.75 x TC - 0.3 0.25 x TC
37.2 --
The number of wait states for out of page access is specified in the DCR. The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. 4 Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states. See Figure 3-16.
Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2
No. Characteristics3 Symbol Expression4 9 x TC 4.75 x TC - 6.5 2.25 x TC - 6.5 3 x TC - 6.5 -- -- 0.0 3.25 x TC - 4.0 5.75 x TC - 4.0 3.25 x TC - 4.0 4.75 x TC - 4.0 2.25 x TC - 4.0 2.5 x TC 2 1.75 x TC 2 4.25 x TC - 4.0 2.75 x TC - 4.0 3.25 x TC - 4.0 36.6 67.9 36.6 55.4 24.1 29.3 19.9 49.1 30.4 36.6 80 MHz Unit Min 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR 112.5 Max -- 52.9 21.6 31.0 -- -- -- -- -- -- 33.3 23.9 -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DSP56362 Technical Data, Rev. 4 3-30 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (continued)
No. Characteristics3 Symbol Expression4 1.75 x TC - 4.0 0.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 4 x TC - 4.0 2 x TC - 3.8 1.25 x TC - 3.7 0.25 x TC - 3.0 3 x TC - 4.2 5.5 x TC - 4.2 8.5 x TC - 4.5 8.75 x TC - 4.3 7.75 x TC - 4.3 4.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 5.5 x TC - 4.3 1.5 x TC - 4.0 1.75 x TC - 4.0 8.5 x TC - 4.0 7.5 x TC - 6.5 0.0 0.75 x TC - 0.3 0.25 x TC 80 MHz Unit Min 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195
1 2
Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 87.3 -- -- 3.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR5 assertion RAS deassertion to WR5 assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance
tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ
17.9 5.4 36.6 67.9 46.0 21.2 11.9 0.1 33.3 64.6 101.8 105.1 92.6 55.4 36.6 67.9 64.5 14.8 17.9 102.3 -- 0.0 9.1 --
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. 4 The asynchronous delays specified in the expressions are valid for DSP56362. 5 Either t RCH or tRRH must be satisfied for read cycles.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-31
External Memory Expansion Port (Port A)
Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2
100 MHz No. Characteristics3 Symbol Expression4 Min 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR5 assertion RAS deassertion to WR5 assertion tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH 4.25 x TC - 4.0 7.75 x TC - 4.0 5.25 x TC - 4.0 6.25 x TC - 4.0 3.75 x TC - 4.0 2.5 x TC 4.0 1.75 x TC 4.0 5.75 x TC - 4.0 4.25 x TC - 4.0 4.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6 x TC - 4.0 3.0 x TC - 4.0 1.75 x TC - 4.0 0.25 x TC - 3.0 0.25 x TC - 2.0 180 181 CAS assertion to WR deassertion RAS assertion to WR deassertion tWCH tWCR 5 x TC - 4.2 7.5 x TC - 4.2 12 x TC 6.25 x TC - 7.0 3.75 x TC - 7.0 4.5 x TC - 7.0 120.0 -- -- -- 0.0 38.5 73.5 48.5 58.5 33.5 21.0 13.5 53.5 38.5 38.5 13.5 3.5 48.5 73.5 56.0 26.0 13.5 -- 0.5 45.8 70.8 Max -- 55.5 30.5 38.0 -- -- -- -- -- -- 29.0 21.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
DSP56362 Technical Data, Rev. 4 3-32 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (continued)
100 MHz No. Characteristics3 Symbol Expression4 Min 182 183 184 185 186 187 188 189 190 191 192 193 194 195
1 2
Unit Max -- -- -- -- -- -- -- -- -- -- 93.0 0.0 -- -- 2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance
tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ
11.5 x TC - 4.5 11.75 x TC - 4.3 10.25 x TC - 4.3 5.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6.5 x TC - 4.3 1.5 x TC - 4.0 2.75 x TC - 4.0 11.5 x TC - 4.0 10 x TC - 7.0
110.5 113.2 103.2 53.5 48.5 73.5 60.7 11.0 23.5 111.0
0.75 x TC - 0.3 0.25 x TC
7.2 --
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. 4 The asynchronous delays specified in the expressions are valid for DSP56362. 5 Either t RCH or tRRH must be satisfied for read cycles.
Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz1, 2 100 MHz No. Characteristics3
Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read)
120 MHz Unit Min
133.3 -- --
Symbol
Expression Min Max
-- 76.8 41.8 49.3
Max
-- 63.0 33.9 40.1 ns ns ns ns
157 158 159 160
tRC tRAC tCAC tAA
16 x TC 8.25 x TC - 5.7 4.75 x TC - 5.7 5.5 x TC - 5.7
160.0 -- -- --
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-33
External Memory Expansion Port (Port A)
Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz1, 2 (continued) 100 MHz No. Characteristics3
CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR4 assertion RAS deassertion to WR4 assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write)
120 MHz Unit Min
0.0
Symbol
Expression Min Max
--
Max
-- ns
161
tOFF
0.0
0.0
162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185
tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS
6.25 x TC - 4.0 9.75 x TC - 4.0 6.25 x TC - 4.0 8.25 x TC - 4.0 4.75 x TC - 4.0 3.5 x TC 2 2.75 x TC 2 7.75 x TC - 4.0 6.25 x TC - 4.0 6.25 x TC - 4.0 2.75 x TC - 4.0 0.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 7 x TC - 4.0 5 x TC - 3.8 1.75 x TC - 3.7 0.25 x TC - 2.0 6 x TC - 4.2 9.5 x TC - 4.2 15.5 x TC - 4.5 15.75 x TC - 4.3 14.25 x TC - 4.3 8.75 x TC - 4.0
58.5 93.5 58.5 78.5 43.5 33.0 25.5 73.5 58.5 58.5 23.5 3.5 58.5 93.5 66.0 46.2 13.8 0.5 55.8 90.8 150.5 153.2 138.2 83.5
-- -- -- -- -- 37.0 29.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
48.1 77.2 48.1 64.7 35.6 27.2 20.9 60.6 48.1 48.1 18.9 2.2 48.1 77.2 54.3 37.9 10.9 0.1 45.8 75.0 124.7 126.9 114.4 68.9
-- -- -- -- -- 31.2 24.9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DSP56362 Technical Data, Rev. 4 3-34 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz1, 2 (continued) 100 MHz No. Characteristics3
CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance
120 MHz Unit Min
48.1 77.2 74.9 8.5 35.6 125.2 -- 0.0 5.9 --
Symbol
Expression Min Max
-- -- -- -- -- -- 134.3 -- -- 2.5
Max
-- -- -- -- -- -- 111.0 -- -- 2.1 ns ns ns ns ns ns ns ns ns ns
186 187 188 189 190 191 192 193 194 195
1 2
tDH tDHR tWCS tCSR tRPC tROH tGA tGZ
6.25 x TC - 4.0 9.75 x TC - 4.0 9.5 x TC - 4.3 1.5 x TC - 4.0 4.75 x TC - 4.0 15.5 x TC - 4.0 14 x TC - 5.7
58.5 93.5 90.7 11.0 43.5 151.0 -- 0.0
0.75 x TC - 0.3 0.25 x TC
7.2 --
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. 4 Either t or tRRH must be satisfied for read cycles. RCH
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-35
External Memory Expansion Port (Port A)
157 162 RAS 167 169 168 170 CAS 171 173 174 175 A0-A17 Row Address 172 177 191 WR 160 159 RD 158 192 Data In AA0476 193 168 179 Column Address 176 166 164 163 165 162
161
D0-D23
Figure 3-17 DRAM Out-of-Page Read Access
DSP56362 Technical Data, Rev. 4 3-36 Freescale Semiconductor
External Memory Expansion Port (Port A)
157 162 163 165 162
RAS 167 169 168 170 CAS 171 173 172
164
166
174 176
A0-A17
Row Address 181
Column Address
175 188 WR 182 180
184 183 RD
187 186 185 194 195
D0-D23
Data Out AA0477
Figure 3-18 DRAM Out-of-Page Write Access
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-37
External Memory Expansion Port (Port A)
157 162 RAS 190 170 CAS 165 163 162
189 177 WR AA0478
Figure 3-19 DRAM Refresh Access
3.10.3
Synchronous Timings (SRAM)
Table 3-17 External Bus Synchronous Timings (SRAM Access)1
100 MHz Unit Min Max 6.5 -- -- -- -- 6.5 -- 2.5 -- -- 11.5 ns ns ns ns ns ns ns ns ns ns ns
No.
Characteristics CLKOUT high to address, and AA valid4 CLKOUT high to address, and AA invalid4 TA valid to CLKOUT high (setup time) CLKOUT high to TA invalid (hold time) CLKOUT high to data out active CLKOUT high to data out valid CLKOUT high to data out invalid CLKOUT high to data out high impedance Data in valid to CLKOUT high (setup) CLKOUT high to data in invalid (hold) CLKOUT high to RD assertion
Expression2, 3 0.25 x TC + 4.0 0.25 x TC
198 199 200 201 202 203 204 205 206 207 208
-- 2.5 4.0 0.0
0.25 x TC 0.25 x TC + 4.0 0.25 x TC 0.25 x TC
2.5 3.3 2.5 -- 4.0 0.0
0.75 x TC + 4.0
8.2
DSP56362 Technical Data, Rev. 4 3-38 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-17 External Bus Synchronous Timings (SRAM Access)1 (continued)
No. Characteristics Expression2, 3 100 MHz Unit Min 209 210 CLKOUT high to RD deassertion CLKOUT high to WR assertion5 0.5 x TC + 4.3 [WS = 1 or WS 4] All frequencies: [2 WS 3] 211
1 2
Max 4.0 9.3 ns ns
0.0 6.3
1.3
4.3
CLKOUT high to WR deassertion
0.0
3.8
ns
External bus synchronous timings should be used only for reference to the clock and not for relative timings. WS is the number of wait states specified in the BCR. 3 The asynchronous delays specified in the expressions are valid for DSP56362. 4 T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR (See T212) to determine whether the access referenced by A0-A23 is internal or external, when this mode is enabled 5 If WS > 1, WR assertion refers to the next rising edge of CLKOUT.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-39
External Memory Expansion Port (Port A)
CLKOUT 198 A0-A17 AA0-AA3 201 200 TA 211 WR 210 203 D0-D23 202 208 RD 207 206 D0-D23 Data In AA0479 209 204 Data Out 205 199
Figure 3-20 Synchronous Bus Timings SRAM 1 WS (BCR Controlled)
DSP56362 Technical Data, Rev. 4 3-40 Freescale Semiconductor
External Memory Expansion Port (Port A)
CLKOUT 198 A0-A17 AA0-AA3 201 200 TA 211 WR 210 203 D0-D23 202 208 RD 207 206 D0-D23 Data In AA0480 209 Data Out 204 205 200 201 199
Figure 3-21 Synchronous Bus Timings SRAM 2 WS (TA Controlled)
3.10.4
Arbitration Timings
Table 3-18 Arbitration Bus Timings1
100 MHz
No.
Characteristics CLKOUT high to BR assertion/deassertion2 BG asserted/deasserted to CLKOUT high (setup) CLKOUT high to BG deasserted/asserted (hold) BB deassertion to CLKOUT high (input setup) CLKOUT high to BB assertion (input hold) CLKOUT high to BB assertion (output)
Expression Min Max 4.0 -- -- -- -- 4.0
Unit
212 213 214 215 216 217
1.0 4.0 0.0 4.0 0.0 1.0
ns ns ns ns ns ns
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-41
External Memory Expansion Port (Port A)
Table 3-18 Arbitration Bus Timings1 (continued)
100 MHz No. Characteristics Expression Min 218 219 220 221 222 223 224
1 2
Unit Max 4.0 4.5 -- 2.5 -- 6.5 7.5 ns ns ns ns ns ns ns
CLKOUT high to BB deassertion (output) BB high to BB high impedance (output) CLKOUT high to address and controls active CLKOUT high to address and controls high impedance CLKOUT high to AA active CLKOUT high to AA deassertion CLKOUT high to AA high impedance 0.25 x TC 0.25 x TC 0.25 x TC 0.25 x TC + 4.0 0.75 x TC
1.0 -- 2.5 -- 2.5 3.2 --
The asynchronous delays specified in the expressions are valid for DSP56362. T212 is valid for Address Trace mode when the ATE bit in the OMR is set. BR is deasserted for internal accesses and asserted for external accesses.
CLKOUT 212 BR 214 213 BG 216 215 BB 220 A0-A17 RD, WR 222 AA0-AA3 AA0481 217
Figure 3-22 Bus Acquisition Timings
DSP56362 Technical Data, Rev. 4 3-42 Freescale Semiconductor
External Memory Expansion Port (Port A)
CLKOUT 212 BR 214 213 BG 219 218 BB 221 A0-A17 RD, WR 224 223 AA0-AA3 AA0482
Figure 3-23 Bus Release Timings Case 1 (BRT Bit in OMR Cleared)
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-43
External Memory Expansion Port (Port A)
CLKOUT 212 BR 214 213 BG 219 218 BB 221 A0-A17 RD, WR 224 223 AA0-AA3 AA0483
Figure 3-24 Bus Release Timings Case 2 (BRT Bit in OMR Set) Table 3-19 Asynchronous Bus Arbitration timing
100 MHz No. Characteristics Expression Min 250 251 BB assertion window from BG input negation. Delay from BB assertion to BG assertion 2 .5* Tc + 5 2 * Tc + 5 -- 20 Max 20 -- ns ns Unit
Notes: 1. Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode 2. At 100 MHz it is recommended to use Asynchronous Arbitration mode. 3. If Asynchronous Arbitration mode is active, none of the timings in Table 3-19 is required. 4. In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in Figure 3-25.
DSP56362 Technical Data, Rev. 4 3-44 Freescale Semiconductor
External Memory Expansion Port (Port A)
BG1
BB 250
BG2 251
Figure 3-25 Asynchronous Bus Arbitration Timing
BG1
BG2
250+251
Figure 3-26 Asynchronous Bus Arbitration Timing
Background explanation for Asynchronous Bus Arbitration: The asynchronous bus arbitration is enabled by internal synchronization circuits on BG, and BB inputs. These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this delay, a 56300 part may assume mastership and assert BB, for some time after BG is negated. This is the reason for timing 250. Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other 56300 components which are potential masters on the same bus. If BG input is asserted before that time, a situation of BG asserted, and BB negated, may cause another 56300 component to assume mastership at the same time. Therefore some non-overlap period between one BG input active to another BG input active, is required. Timing 251 ensures that such a situation is avoided.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-45
Parallel Host Interface (HDI08) Timing
3.11
Parallel Host Interface (HDI08) Timing
Table 3-20 Host Interface (HDI08) Timing1, 2 100 MHz Min
19.9
No.
317
Characteristics3
Read data strobe assertion width4 HACK read assertion width
Expression
TC + 9.9
Max
--
Unit
ns
318
Read data strobe deassertion width4 HACK read deassertion width
--
9.9
--
ns
319
Read data strobe deassertion width4 after "Last Data Register" reads5, 6, or between two consecutive CVR, ICR, or ISR reads7 HACK deassertion width after "Last Data Register" reads5, 6
2.5 x TC + 6.6
31.6
--
ns
320 321
Write data strobe assertion width8HACK write assertion width Write data strobe deassertion width8 HACK write deassertion width after ICR, CVR and "Last Data Register" writes5 after IVR writes, or after TXH:TXM writes (with HBE=0), or after TXL:TXM writes (with HBE=1)
-- 2.5 x TC + 6.6
13.2 31.6
-- --
ns ns
16.5
--
322 323 324
HAS assertion width HAS deassertion to data strobe assertion9 Host data input setup time before write data strobe deassertion8 Host data input setup time before HACK write deassertion
-- -- --
9.9 0.0 9.9
-- -- --
ns ns ns
325
Host data input hold time after write data strobe deassertion8 Host data input hold time after HACK write deassertion
--
3.3
--
ns
326
Read data strobe assertion to output data active from high impedance4 HACK read assertion to output data active from high impedance
--
3.3
--
ns
327
Read data strobe assertion to output data valid4 HACK read assertion to output data valid
--
--
24.2
ns
328
Read data strobe deassertion to output data high impedance4 HACK read deassertion to output data high impedance Output data hold time after read data strobe deassertion4 Output data hold time after HACK read deassertion
--
--
9.9
ns
329
--
3.3
--
ns
330 331 332
HCS assertion to read data strobe deassertion4 HCS assertion to write data strobe deassertion8 HCS assertion to output data valid
TC +9.9 -- --
19.9 9.9 --
-- -- 19.1
ns ns ns
DSP56362 Technical Data, Rev. 4 3-46 Freescale Semiconductor
Parallel Host Interface (HDI08) Timing
Table 3-20 Host Interface (HDI08) Timing1, 2 (continued) No.
333 334
Characteristics
3
Expression
-- --
100 MHz Min
0.0 4.7
Max
-- --
Unit
ns ns
HCS hold time after data strobe deassertion9 Address (AD7-AD0) setup time before HAS deassertion (HMUX=1) Address (AD7-AD0) hold time after HAS deassertion (HMUX=1) A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W setup time before data strobe assertion9 * Read * Write
335 336
-- --
3.3
--
ns ns
0 4.7 -- 3.3
-- -- -- ns
337
A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W hold time after data strobe deassertion9 Delay from read data strobe deassertion to host request assertion for "Last Data Register" read4, 5, 10 Delay from write data strobe deassertion to host request assertion for "Last Data Register" write5, 8, 10 Delay from data strobe assertion to host request deassertion for "Last Data Register" read or write (HROD = 0)5, 9, 10 Delay from data strobe assertion to host request deassertion for "Last Data Register" read or write (HROD = 1, open drain Host Request)5, 9, 10, 11 Delay from DMA HACK deassertion to HOREQ assertion * For "Last Data Register" read * For "Last Data Register" * For other cases
5
338
TC 2 x TC --
10
--
ns
339
20
--
ns
340
--
19.1
ns
341
--
--
300.0
ns
ns
342
2 x TC + 19.1 1.5 x TC + 19.1
39.1 34.1 0.0
-- -- -- ns
write5
343
Delay from DMA HACK assertion to HOREQ deassertion * HROD = 05
-- -- -- -- 300.0 20.2
344
Delay from DMA HACK assertion to HOREQ deassertion for "Last Data Register" read or write * HROD = 1, open drain Host Request5, 11
ns
1 2 3 4 5 6 7
See Host Port Usage Considerations in the DSP56362 User Design Manual. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. VCC = 3.3 V 0.16 V; TJ = 0C to +100C, CL = 50 pF The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode. The "last data register" is the register at address $7, which is the last location to be read or written in data transfers. This is RXL/TXL in the little endian mode (HBE = 0), or RXH/TXH in the big endian mode (HBE = 1). This timing is applicable only if a read from the "last data register" is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal. This timing is applicable only if two consecutive reads from one of these registers are executed.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-47
Parallel Host Interface (HDI08) Timing
8 9
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data strobe mode. 10 The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. 11 In this calculation, the host request signal is pulled up by a 4.7 k resistor in the open-drain mode.
317 HACK 327 326 HD7-HD0 329 328
318
HOREQ AA1105
Figure 3-27 Host Interrupt Vector Register (IVR) Read Timing Diagram
HA0-HA2 336 330 HCS 337 333
317 HRD, HDS 318 328 332 327 326 HD0-HD7 340 341 HOREQ, HRRQ, HTRQ 338 319 329
AA0484
Figure 3-28 Read Timing Diagram, Non-Multiplexed Bus
DSP56362 Technical Data, Rev. 4 3-48 Freescale Semiconductor
Parallel Host Interface (HDI08) Timing
HA0-HA2 336 331 333 HCS 337
320 HWR, HDS 321 324 325 HD0-HD7 340 341 HOREQ, HRRQ, HTRQ AA0485 339
Figure 3-29 Write Timing Diagram, Non-Multiplexed Bus
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-49
Parallel Host Interface (HDI08) Timing
HA8-HA10 336 322 HAS 323 337
317 HRD, HDS 334 335 327 328 329 HAD0-HAD7 Address 326 340 341 HOREQ, HRRQ, HTRQ AA0486 338 Data 318 319
Figure 3-30 Read Timing Diagram, Multiplexed Bus
DSP56362 Technical Data, Rev. 4 3-50 Freescale Semiconductor
Parallel Host Interface (HDI08) Timing
HA8-HA10 336
322 HAS
323
320 HWR, HDS 334 335 HAD0-HAD7 Address Data 340 341 HOREQ, HRRQ, HTRQ AA0487 339 324 321 325
Figure 3-31 Write Timing Diagram, Multiplexed Bus
HOREQ (Output)
343 344 320 342
321
HACK (Input)
TXH/M/L Write 324 325
H0-H7 (Input)
Data Valid
Figure 3-32 Host DMA Write Timing Diagram
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-51
Serial Host Interface SPI Protocol Timing
HOREQ (Output)
343 342 317 318 342
HACK (Input)
RXH Read 327 328 329 Data Valid
H0-H7 (Output)
326
Figure 3-33 Host DMA Read Timing Diagram
3.12
Serial Host Interface SPI Protocol Timing
Table 3-21 Serial Host Interface SPI Protocol Timing
100MHz
No. 140
Characteristics Tolerable spike width on clock or data in
Mode --
Filter Mode Bypassed Narrow Wide
Expression Min -- -- -- -- 6xTC+46 6xTC+152 6xTC+223 0.5xtSPICC -10 0.5xtSPICC -10 0.5xtSPICC -10 2.5xTC+12 2.5xTC+102 2.5xTC+189 0.5xtSPICC -10 0.5xtSPICC -10 0.5xtSPICC -10 2.5xTC+12 2.5xTC+102 2.5xTC+189 106 212 283 43 96 131 37 127 214 43 96 131 37 127 214 Max 0 50 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit ns
141
Minimum serial clock cycle = tSPICC(min)
Master
Bypassed Narrow Wide
ns
142
Serial clock high period
Master
Bypassed Narrow Wide
ns
Slave
Bypassed Narrow Wide
143
Serial clock low period
Master
Bypassed Narrow Wide
ns
Slave
Bypassed Narrow Wide
DSP56362 Technical Data, Rev. 4 3-52 Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
Table 3-21 Serial Host Interface SPI Protocol Timing (continued)
100MHz No. 144 Characteristics Serial clock rise/fall time Mode Master Slave 146 SS assertion to first SCK edge CPHA = 0 Slave Filter Mode -- -- Bypassed Narrow Wide CPHA = 1 Slave Bypassed Narrow Wide 147 Last SCK edge to SS not asserted slave Bypassed Narrow Wide 148 Data input valid to SCK edge (data input set-up time) Master/ Slave Bypassed Narrow Wide 149 SCK last sampling edge to data input not valid Master/ Slave Bypassed Narrow Wide 150 151 152 SS assertion to data out active SS deassertion to data high impedance SCK edge to data out valid (data out delay time) Slave Slave Master/ Slave -- -- Bypassed Narrow Wide 153 SCK edge to data out not valid (data out hold time) Master/ Slave Bypassed Narrow Wide 154 157 SS assertion to data out valid (CPHA = 0) First SCK sampling edge to HREQ output deassertion Slave Slave -- Bypassed Narrow Wide 158 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave Bypassed Narrow Wide Expression Min -- -- 3.5xTC+15 0 0 10 0 0 12 102 189 0 MAX{(20-TC), 0} MAX{(40-TC), 0} 2.5xTC+10 2.5xTC+30 2.5xTC+50 2 9 2xTC+33 2xTC+123 2xTC+210 TC+5 TC+55 TC+106 TC+33 2.5xTC+30 2.5xTC+120 2.5xTC+217 2.5xTC+30 2.5xTC+80 2.5xTC+136 -- -- 50 0 0 10 0 0 12 102 189 0 10 30 35 55 75 2 -- -- -- -- 15 65 116 -- -- -- -- 55 105 161 Max 10 2000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 53 143 230 -- -- -- 43 55 145 242 -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns Unit
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-53
Serial Host Interface SPI Protocol Timing
Table 3-21 Serial Host Interface SPI Protocol Timing (continued)
100MHz No. 159 Characteristics SS deassertion to HREQ output not deasserted (CPHA = 0) SS deassertion pulse width (CPHA = 0) HREQ in assertion to first SCK edge Mode Slave Filter Mode -- Expression Min 2.5xTC+30 TC+6 0.5 x tSPICC + 2.5xTC+43 0.5 xtSPICC + 2.5xTC+43 0.5 xtSPICC + 2.5xTC+43 0 55 Max -- ns Unit
160 161
Slave Master
-- Bypassed Narrow Wide
16 121 174 209
-- -- -- --
ns ns
162
HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) First SCK edge to HREQ in not asserted (HREQ in hold time)
Master
--
0
--
ns
163
Master
--
0
0
--
ns
Note: Periodically sampled, not 100% tested
SS (Input) 143 142 SCK (CPOL=0 (Output) 142 SCK (CPOL = 1 (Output) 148 149 MISO (Input) MSB Valid 152 MOSI (Output) 161 163 HREQ (Input) AA0271 MSB 143 141 144 144 144 141 144
148 LSB Valid 153 LSB
149
Figure 3-34 SPI Master Timing (CPHA = 0)
DSP56362 Technical Data, Rev. 4 3-54 Freescale Semiconductor
Serial Host Interface SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0 (Output) 142 SCK (CPOL = 1 (Output) 143 144 141 144 144 141 144
148 149 MISO (Input) MSB Valid 152 MOSI (Output) 161 163 HREQ (Input) MSB 162 LSB Valid 153
148 149
LSB
AA0272
Figure 3-35 SPI Slave Timing (CPHA = 0)
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-55
Serial Host Interface SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0 (Output) 142 SCK (CPOL = 1 (Output) 143 144 141 144 144 141 144
148 149 MISO (Input) MSB Valid 152 MOSI (Output) 161 163 HREQ (Input) MSB 162 LSB Valid 153
148 149
LSB
AA0272
Figure 3-36 SPI Master Timing (CPHA = 1)
DSP56362 Technical Data, Rev. 4 3-56 Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 142 143 141 144 144 144 141 144 160 147
154 150 MISO (Output) 148 149 MOSI (Input) MSB Valid 157 HREQ (Output) 153 MSB
152
153
151 LSB 148 149 LSB Valid 159
AA0273
Figure 3-37 SPI Slave Timing (CPHA = 0)
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-57
Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 142 143 144 144 144 141 144 147
152 150 MISO (Output) 148
152
153
151 LSB 148
MSB
149 MOSI (Input) MSB Valid 157 HREQ (Output) LSB Valid
149
158
AA0274
Figure 3-38 SPI Slave Timing (CPHA = 1)
DSP56362 Technical Data, Rev. 4 3-58 Freescale Semiconductor
Serial Host Interface (SHI) I2C Protocol Timing
3.13
Serial Host Interface (SHI) I2C Protocol Timing
Table 3-22 SHI I2C Protocol Timing
Standard I2C* Symbol/ Expression -- -- -- -- FSCL TBUF TSU;STA THD;STA TLOW THIGH TR TF TSU;DAT THD;DAT TSU;STO Cb FDSP 10.6 11.8 13.1 tSU;RQI 0.0 -- -- -- -- 28.5 39.7 61.0 0.0 -- -- -- -- ns -- 4.7 4.7 4.0 4.7 4.0 -- -- 250 0.0 4.0 -- 0 50 100 100 -- -- -- -- -- 1000 300 -- -- -- 400 -- -- -- -- 1.3 0.6 0.6 1.3 1.3 20 + 0.1 x Cb 20 + 0.1 x Cb 100 0.0 0.6 -- 0 50 100 400 -- -- -- -- -- 300 300 -- 0.9 -- 400 kHz s s s s s ns ns ns s s pF MHz Standard Min Max Fast-Mode Min Max ns Unit
No.
Characteristics
Tolerable spike width on SCL or SDA Filters bypassed Narrow filters enabled Wide filters enabled 171 172 173 174 175 176 177 178 179 180 181 182 183 SCL clock frequency Bus free time Start condition set-up time Start condition hold time SCL low period SCL high period SCL and SDA rise time SCL and SDA fall time Data set-up time Data hold time Stop condition set-up time Capacitive load for each line DSP clock frequency Filters bypassed Narrow filters enabled Wide filters enabled 184 HREQ in deassertion to last SCL edge (HREQ in set-up time) First SCL sampling edge to HREQ output deassertion Filters bypassed Narrow filters enabled Wide filters enabled
186
TNG;RQO 2 x TC + 30 2 x TC + 120 2 x TC + 208 -- -- -- 50 140 228 -- -- -- 50 140 228
ns
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-59
Serial Host Interface (SHI) I2C Protocol Timing
Table 3-22 SHI I2C Protocol Timing (continued)
Standard I2C* Symbol/ Expression TAS;RQO 2 x TC + 30 2 x TC + 80 2 x TC + 135 TAS;RQI 0.5 x TI2CCP -- 0.5 x TC - 21 4327 4282 4238 -- -- -- 927 882 838 -- -- -- 50 100 155 -- -- -- 50 100 155 -- -- -- ns Standard Min Max Fast-Mode Min Max ns Unit
No.
Characteristics
187
Last SCL edge to HREQ output not deasserted Filters bypassed Narrow filters enabled Wide filters enabled
188
HREQ in assertion to first SCL edge Filters bypassed Narrow filters enabled Wide filters enabled
Note: RP (min) = 1.5 k3/4
3.13.1
Programming the Serial Clock
The programmed serial clock cycle, T I2CCP, is specified by the value of the HDM[5:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I2CCP is T where: HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected. In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x T C ( if HDM [ 5 :0 ] = $02 and HRS = 1 ) to 4096 x T C ( if HDM [ 7 :0 ] = $FF and HRS = 0 ) The programmed serial clock cycle (TI2CCP ), SCL rise time (TR), and the filters selected should be chosen in order to achieve the desired SCL frequency, as shown in Table 3-23
I CCP
2
= [ T C x 2 x ( HDM [ 7 :0 ] + 1 ) x ( 7 x ( 1 - HRS ) + 1 ) ]
DSP56362 Technical Data, Rev. 4 3-60 Freescale Semiconductor
Serial Host Interface (SHI) I2C Protocol Timing
.
Table 3-23 SCL Serial Clock Cycle generated as Master
Filters bypassed Narrow filters enabled Wide filters enabled TI2CCP + 2.5 x TC + 45ns + TR TI2CCP + 2.5 x TC + 135ns + TR TI2CCP + 2.5 x TC + 223ns + TR
EXAMPLE:
For DSP clock frequency of 100 MHz (i.e. TC = 10ns), operating in a standard-mode I2C environment (FSCL = 100 KHz (i.e. TSCL = 10s), TR = 1000ns), with filters bypassed T
I CCP
2
= 10s - 2.5 x 10ns - 45ns - 1000ns = 8930ns
Choosing HRS = 0 gives HDM [ 7 :0 ] = 8930ns ( 2 x 10ns x 8 ) - 1 = 55.8 Thus the HDM[7:0] value should be programmed to $38 (=56).
171 173 SCL 177 172 179 SDA Stop Start 174 189 188 HREQ AA0275 MSB 186 184 187 LSB 182 ACK 183 Stop 178 180 176 175
Figure 3-39 I2C Timing
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-61
Enhanced Serial Audio Interface Timing
3.14
Enhanced Serial Audio Interface Timing
Table 3-24 Enhanced Serial Audio Interface Timing
100 MHz Symbol Expression Min Max -- -- i ck x ck x ck ns 2 x TC - 10.0 1.5 x TC -- 2 x TC - 10.0 1.5 x TC -- -- 10.0 15.0 -- -- -- -- 37.0 22.0 37.0 22.0 39.0 24.0 39.0 -- 24.0 36.0 21.0 37.0 22.0 -- -- -- -- -- -- -- -- x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a ns ns ns ns ns ns ns ns ns ns 10.0 15.0 -- -- ns ns Condition4 Unit
No. 430 Clock cycle5
Characteristics1, 2, 3
tSSICC
4 x TC RXC:3 xTC TXC:MAX [3xTC;t454]
40.0 30 40
431 Clock high period * For internal clock * For external clock 432 Clock low period * For internal clock * For external clock 433 RXC rising edge to FSR out (bl) high
--
434 RXC rising edge to FSR out (bl) low
--
--
-- --
435 RXC rising edge to FSR out (wr) high6
--
--
-- --
436 RXC rising edge to FSR out (wr) low6
--
--
437 RXC rising edge to FSR out (wl) high
--
--
-- --
438 RXC rising edge to FSR out (wl) low
--
--
-- --
439 Data in setup time before RXC (TXC in synchronous mode) falling edge 440 Data in hold time after RXC falling edge
--
--
0.0 19.0
--
--
5.0 3.0
441 FSR input (bl, wr) high before RXC falling edge6
--
--
23.0 1.0
442 FSR input (wl) high before RXC falling edge
--
--
1.0 23.0
DSP56362 Technical Data, Rev. 4 3-62 Freescale Semiconductor
Enhanced Serial Audio Interface Timing
Table 3-24 Enhanced Serial Audio Interface Timing (continued)
No. Characteristics1, 2, 3 100 MHz Symbol Expression Min 443 FSR input hold time after RXC falling edge -- -- 3.0 0.0 444 Flags input setup before RXC falling edge -- -- 0.0 19.0 445 Flags input hold time after RXC falling edge -- -- 6.0 0.0 446 TXC rising edge to FST out (bl) high -- -- -- -- 447 TXC rising edge to FST out (bl) low -- -- -- -- 448 TXC rising edge to FST out (wr) high6 -- -- -- -- 449 TXC rising edge to FST out (wr) low6 -- -- -- -- 450 TXC rising edge to FST out (wl) high -- -- -- -- 451 TXC rising edge to FST out (wl) low -- -- -- -- 452 TXC rising edge to data out enable from high impedance 453 TXC rising edge to transmitter drive enable assertion 454 TXC rising edge to data out valid -- -- -- -- -- -- -- -- -- 23 + 0.5 x TC 21.0 -- -- 455 TXC rising edge to data out high impedance7 -- -- -- -- 456 TXC rising edge to transmitter drive enable deassertion7 457 FST input (bl, wr) setup time before TXC falling edge6 -- -- -- -- -- -- 2.0 21.0 Max -- -- -- -- -- -- 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 28.0 21.0 31.0 16.0 34.0 20.0 -- -- x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Condition4 Unit
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-63
Enhanced Serial Audio Interface Timing
Table 3-24 Enhanced Serial Audio Interface Timing (continued)
No. Characteristics1, 2, 3 100 MHz Symbol Expression Min 458 FST input (wl) to data out enable from high impedance 459 FST input (wl) to transmitter drive enable assertion 460 FST input (wl) setup time before TXC falling edge 461 FST input hold time after TXC falling edge -- -- -- Max 27.0 -- ns Condition4 Unit
--
--
--
31.0
--
ns
--
--
2.0 21.0
-- -- -- -- 32.0 18.0 -- 27.5 27.5
x ck i ck x ck i ck x ck i ck
ns
--
--
4.0 0.0
ns
462 Flag output valid after TXC rising edge
--
--
-- --
ns
463 HCKR/HCKT clock cycle 464 HCKT input rising edge to TXC output 465 HCKR input rising edge to RXC output
1 2
-- -- --
-- -- --
40.0 -- --
ns ns ns
3
4
5 6
7
VCC = 3.3 V 0.16 V; TJ = 0C to +100C, CL = 50 pF i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length wr = word length relative TXC(SCKT pin) = transmit clock RXC(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock For the internal clock, the clock cycle at the pin is defined by Icyc and the ESAI control registers. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. Periodically sampled and not 100% tested.
DSP56362 Technical Data, Rev. 4 3-64 Freescale Semiconductor
Enhanced Serial Audio Interface Timing
430 TXC (Input/Output) 431 432
446 FST (Bit) Out
447
450 FST (Word) Out 454 452 Data Out First Bit 459 Last Bit 454
451
455
Transmitter Drive Enable
FST (Bit) In
457 461
453
456
FST (Word) In
458 460 461
Flags Out
462
See Note
Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. AA0490
Figure 3-40 ESAI Transmitter Timing
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-65
Enhanced Serial Audio Interface Timing
430 431 RXC (Input/Output) 433 FSR (Bit) Out 437 438 432
434
FSR (Word) Out
440 Data In 439 First Bit FSR (Bit) In 441 443 Last Bit
FSR (Word) In
442
443
Flags In
444
445
AA0491
Figure 3-41 ESAI Receiver Timing
HCKT
SCKT(output)
463
464
Figure 3-42 ESAI HCKT Timing
DSP56362 Technical Data, Rev. 4 3-66 Freescale Semiconductor
Digital Audio Transmitter Timing
HCKR
SCKR (output)
463
465
Figure 3-43 ESAI HCKR Timing
3.15
Digital Audio Transmitter Timing
Table 3-25 Digital Audio Transmitter Timing
100 MHz
No.
Characteristic ACI frequency1
Expression Min -- 2 x TC 0.5 x TC 0.5 x TC 1.5 x TC -- 20 5 5 -- Max 50 -- -- -- 15
Unit
MHz ns ns ns ns
220 221 222 223
1
ACI period ACI high duration ACI low duration ACI rising edge to ADO valid
In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56362 internal clock frequency. For example, if the DSP56362 is running at 100 MHz internally, the ACI frequency should be less than 50 MHz.
ACI 220 223 ADO AA1280 221 222
Figure 3-44 Digital Audio Transmitter Timing
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-67
Timer Timing
3.16
Timer Timing
Table 3-26 Timer Timing1
100 MHz
No.
Characteristics
Expression Min Max -- -- 10.0 -- 2 x TC + 2.0 2 x TC + 2.0
Unit
480 481 482 483
TIO Low TIO High Timer setup time from TIO (Input) assertion to CLKOUT rising edge Synchronous timer delay time from CLKOUT rising edge to the external memory access address out valid caused by first interrupt instruction execution CLKOUT rising edge to TIO (Output) assertion * Minimum * Maximum
22.0 22.0 9.0
ns ns ns ns
10.25 x TC + 1.0
103.5
484
ns 0.5 x TC + 3.5 0.5 x TC + 19.8 8.5 -- -- 24.8 ns 0.5 x TC + 3.5 0.5 x TC + 19.0 8.5 -- -- 24.8
485
CLKOUT rising edge to TIO (Output) deassertion * Minimum * Maximum
1
VCC = 3.3 V 0.16 V; TJ = 0C to +100C, CL = 50 pF
TIO 480 481 AA0492
Figure 3-45 TIO Timer Event Input Restrictions
CLKOUT
TIO (Input) 482
Address 483 First Interrupt Instruction Execution AA0493
Figure 3-46 Timer Interrupt Generation
DSP56362 Technical Data, Rev. 4 3-68 Freescale Semiconductor
GPIO Timing
CLKOUT
TIO (Output) 484 485 AA0494
Figure 3-47 External Pulse Generation
3.17
GPIO Timing
Table 3-27 GPIO Timing1
100 MHz
No.
Characteristics
Expression Min Max 31.0 -- -- -- -- 13 13
Unit
490 491 492 493 494 495 496
1
CLKOUT edge to GPIO out valid (GPIO out delay time) CLKOUT edge to GPIO out not valid (GPIO out hold time) GPIO In valid to CLKOUT edge (GPIO in set-up time) CLKOUT edge to GPIO in not valid (GPIO in hold time) Fetch to CLKOUT edge before GPIO change GPIO out rise time GPIO out fall time 6.75 x TC -- --
-- 3.0 12.0 0.0 67.5 -- --
ns ns ns ns ns ns ns
VCC = 3.3 V 0.16 V; TJ = 0C to +100C, CL = 50 pF
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-69
JTAG Timing
CLKOUT (Output) 490 491 GPIO (Output) 492 GPIO (Input) Valid 493
A0-A17 494 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. GPIO (Output) 495 496
AA0495
Figure 3-48 GPIO Timing
3.18
JTAG Timing
Table 3-28 JTAG Timing1, 2
All Frequencies
No.
Characteristics Min Max 22.0 -- -- 3.0 -- -- 40.0 40.0 TCK frequency of operation (1/(TC x 3); maximum 22 MHz) TCK cycle time in Crystal mode TCK clock pulse width measured at 1.5 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance
Unit
500 501 502 503 504 505 506 507
0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0
MHz ns ns ns ns ns ns ns
DSP56362 Technical Data, Rev. 4 3-70 Freescale Semiconductor
JTAG Timing
Table 3-28 JTAG Timing1, 2 (continued)
All Frequencies No. Characteristics Min 508 509 510 511 512 513
1 2
Unit Max -- -- 44.0 44.0 -- -- ns ns ns ns ns ns
TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST setup time to TCK low
5.0 25.0 0.0 0.0 100.0 40.0
VCC = 3.3 V 0.16V; TJ = 0C to +100C, CL = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
501 502 TCK (Input) VIH 503 VM VIL 503 502 VM
AA0496
Figure 3-49 Test Clock Input Timing Diagram
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-71
JTAG Timing
TCK (Input)
VIH VIL 504 505
Data Inputs 506 Data Outputs 507 Data Outputs 506 Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid AA0497
Figure 3-50 Boundary Scan (JTAG) Timing Diagram
TCK (Input) TDI TMS (Input)
VIH VIL 508 Input Data Valid 510 509
TDO (Output) 511 TDO (Output) 510 TDO (Output)
Output Data Valid
Output Data Valid AA0498
Figure 3-51 Test Access Port Timing Diagram
DSP56362 Technical Data, Rev. 4 3-72 Freescale Semiconductor
OnCE Module TimIng TCK (Input) 513 TRST (Input) 512 AA0499
Figure 3-52 TRST Timing Diagram
3.19
OnCE Module TimIng
Table 3-29 OnCE Module Timing1
100 MHz
No.
Characteristics
Expression Min Max 22.0 1/(TC x 3), max 22.0 MHz
Unit
500
TCK frequency of operation
0.0
MHz
514 515
DE assertion time in order to enter Debug mode Response time when DSP56362 is executing NOP instructions from internal memory Debug acknowledge assertion time
1.5 x TC + 10.0 5.5 x TC + 30.0 3 x TC + 10.0
25.0 --
-- 85.0
ns ns
516
1
40.0
--
ns
VCC = 3.3 V 0.16 V; TJ = 0C to +100C, CL = 50 pF
DE 514 515 516 AA0500
Figure 3-53 OnCE--Debug Request
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-73
OnCE Module TimIng
NOTES
DSP56362 Technical Data, Rev. 4 3-74 Freescale Semiconductor
4
4.1
Packaging
Pin-out and Package Information
This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 2, "Signal/Connection Descriptions" are allocated for the package. The DSP56362 is available in a 144-pin LQFP package.
4.2
LQFP Package Description
Top view of the LQFP package is shown in Figure 4-1 with its pin-outs. The LQFP package mechanical drawing is shown in Figure 4-2.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 4-1
LQFP Package Description
A14 A13 A12 VCCQL
VCCQH
D6 D5 D4 D3 GNDD
D2 D1 D0 A17 A16 A15 GNDA
GNDQ
A11 A10 GNDA
A9 A8 A7 A6 GNDA
A5 A4 A3 A2 GNDA
VCCD
VCCA
VCCA
VCCA
73
A1
D7 D8 VCCD GNDD D9 D10 D11 D12 D13 D14 VCCD GNDD D15 D16 D17 D18 D19
109
(Top View)
A0 BG AA0 AA1 RD WR GNDC VCCC BB BR TA PINIT nc CLKOUT GNDC VCCC VCCQL EXTAL GNDQ
VCCQL
GNDQ D20 VCCD GNDD D21 D22 D23 MODD MODC MODB MODA
DSP56362
DE
CAS AA2 AA3 VCCQH GNDP1 GNDP PCAP VCCP RESET HAD0 HAD1 HAD2 HAD3 GNDH VCCH HAD4
TRST
TDO TDI TCK TMS MOSI MISO
Orientation Mark
1
37
HACK HOREQ
SS HREQ
SDO1
HDS
SDO2 SDO3 VCCS GNDS SDO4 SDO5 FST FSR SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH
VCCS GNDS ADO ACI TIO0
HCS
SDO0
Note: Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table and Table 4-2 for detailed information about pin functions and signal names.
HA9 HA8 HAS HAD7 HAD6 HAD5
SCK
HRW
4-1
AA0301
Figure 4-1 DSP56362 Thin Quad Flat Pack (LQFP), Top View
DSP56362 Technical Data, Rev. 4 4-2 Freescale Semiconductor
LQFP Package Description
Table 4-1 DSP56362 LQFP Signal Identification by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Signal Name1 SCK/SCL SS/HA2 HREQ SDO0 or PC11 SDO1 or PC10 SDO2/SDI3 or PC9 SDO3/SDI2 or PC8 VCCS GNDS SDO4/SDI1 or PC7 SDO5/SDI0 or PC6 FST or PC4 FSR or PC1 SCKT or PC3 SCKR or PC0 HCKT or PC5 HCKR or PC2 VCCQL GNDQ VCCQH HDS/HDS, HWR/HWR, or PB12 HRW, HRD/HRD, or PB11 HACK/HACK, HRRQ/HRRQ, or PB15 HOREQ/HOREQ, HTRQ/HTRQ, or PB14 VCCS Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 GNDS ADO or PD1 ACI or PD0 TIO0 HCS/HCS, HA10, or PB13 HA2, HA9, or PB10 HA1, HA8, or PB9 HA0, HAS/HAS, or PB8 H7, HAD7, or PB7 H6, HAD6, or PB6 H5, HAD5, or PB5 H4, HAD4, or PB4 VCCH GNDH H3, HAD3, or PB3 H2, HAD2, or PB2 H1, HAD1, or PB1 H0, HAD0, or PB0 RESET VCCP PCAP Signal Name1 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Signal Name1 AA2/RAS2 CAS DE GNDQ EXTAL VCCQL VCCC GNDC CLKOUT NC (not connected) PINIT/NMI TA BR BB VCCC GNDC WR RD AA1/RAS1 AA0/RAS0 BG
22 23
47 48
GNDP GNDP1
72 73
A0 A1
24
49
VCCQH
74
VCCA
25
50
AA3/RAS3
75
GNDA
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 4-3
LQFP Package Description
Table 4-1 DSP56362 LQFP Signal Identification by Pin Number (continued)
Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
1
Signal Name1 A2 A3 A4 A5 VCCA GNDA A6 A7 A8 A9 VCCA GNDA A10 A11 GNDQ VCCQL A12 A13 A14 VCCQH GNDA A15 A16
Pin No. 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 A17 D0 D1 D2 VCCD GNDD D3 D4 D5 D6 D7 D8 VCCD GNDD D9 D10 D11 D12 D13 D14 VCCD GNDD D15
Signal Name1
Pin No. 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 D16 D17 D18 D19 VCCQL GNDQ D20 VCCD GNDD D21 D22 D23
Signal Name1
MODD/IRQD MODC/IRQC MODB/IRQB MODA/IRQA TRST TDO TDI TCK TMS MOSI/HA0 MISO/SDA
Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted, but act as interrupt lines during operation. Some signals have configurable polarity; these names are shown with and without overbars, such as HAS/HAS. Some pins have two or more configurable functions; names assigned to these pins indicate the function for a specific configuration. For example, pin 34 is data line H7 in nonmultiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin.
DSP56362 Technical Data, Rev. 4 4-4 Freescale Semiconductor
LQFP Package Description
Table 4-2 DSP56362 LQFP Signal Identification by Name
Signal Name not connected A0 A1 A10 A11 A12 A13 A14 A15 A16 A17 A2 A3 A4 A5 A6 A7 A8 A9 AA0 AA1 AA2 AA3 ACI ADO BB BG Pin No. 60 72 73 88 89 92 93 94 97 98 99 76 77 78 79 82 83 84 85 70 69 51 50 28 27 64 71 Signal Name D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D3 D4 D5 D6 D7 D8 D9 DE EXTAL FSR FST GNDA GNDA GNDA GNDA Pin No. 117 118 121 122 123 124 125 102 128 131 132 133 105 106 107 108 109 110 113 53 55 13 12 75 81 87 96 Signal Name GNDP1 GNDQ GNDQ GNDQ GNDQ GNDS GNDS H0 H1 H2 H3 H4 H5 H6 H7 HA0 HA0 HA1 HA10 HA2 HA2 HA8 HA9 HACK/HACK HAD0 HAD1 HAD2 Pin No. 48 19 54 90 127 9 26 43 42 41 40 37 36 35 34 33 143 32 30 2 31 32 31 23 43 42 41
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 4-5
LQFP Package Description
Table 4-2 DSP56362 LQFP Signal Identification by Name (continued)
Signal Name BR CAS CLKOUT D0 D1 D10 D11 D12 HOREQ/HOREQ HRD/HRD HREQ HRRQ/HRRQ HRW HCKR HCKT HTRQ/HTRQ HWR/HWR IRQA IRQB IRQC IRQD MISO MODA MODB MODC MODD MOSI Pin No. 63 52 59 100 101 114 115 116 24 22 3 23 22 17 16 24 21 137 136 135 134 144 137 136 135 134 143 Signal Name GNDC GNDC GNDD GNDD GNDD GNDD GNDH GNDP PB9 PC0 PC1 PC10 PC11 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PCAP PD0 PD1 PINIT RAS0 RAS1 Pin No. 58 66 104 112 120 130 39 47 32 15 13 5 4 17 14 12 16 11 10 7 6 46 28 27 61 70 69 Signal Name HAD3 HAD4 HAD5 HAD6 HAD7 HAS/HAS HCS/HCS HDS/HDS SDO3 SDO4 SDO5 SS TA TCK TDI TDO TIO0 TMS TRST VCCA VCCA VCCA VCCC VCCC VCCD VCCD VCCD Pin No. 40 37 36 35 34 33 30 21 7 10 11 2 62 141 140 139 29 142 138 74 80 86 57 65 103 111 119
DSP56362 Technical Data, Rev. 4 4-6 Freescale Semiconductor
LQFP Package Description
Table 4-2 DSP56362 LQFP Signal Identification by Name (continued)
Signal Name NMI PB0 PB1 PB10 PB11 PB12 PB13 PB14 PB15 PB2 PB3 PB4 PB5 PB6 PB7 PB8 Pin No. 61 43 42 31 22 21 30 24 23 41 40 37 36 35 34 33 Signal Name RAS2 RAS3 RD RESET SCK SCKR SCKT SCL SDA SDI0 SDI1 SDI2 SDI3 SDO0 SDO1 SDO2 Pin No. 52 51 68 44 1 15 14 1 144 11 10 7 6 4 5 6 Signal Name VCCD VCCH VCCP VCCQH VCCQH VCCQH VCCQL VCCQL VCCQL VCCQL VCCS VCCS WR Pin No. 129 38 45 20 49 95 18 56 91 126 8 25 67
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 4-7
LQFP Package Mechanical Drawing
4.3
LQFP PACKAGE MECHANICAL DRAWING
Figure 4-2 DSP56362 144-pin LQFP Package
DSP56362 Technical Data, Rev. 4 4-8 Freescale Semiconductor
5
5.1
Design Considerations
Thermal Design Considerations
T J = T A + ( P D x R JA )
An estimation of the chip junction temperature, TJ, in C can be obtained from the following equation:
Where: TA PD = ambient temperature C = power dissipation in package W RJA = package junction-to-ambient thermal resistance C/W Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance. R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 5-1
Electrical Design Considerations
*
* *
To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD.
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
5.2
Electrical Design Considerations
CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 k ohm.
Use the following list of recommendations to assure correct DSP operation: * Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. * Use at least six 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. * Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 1.2 cm (0.5 inch) per capacitor lead. * Use at least a four-layer PCB with two inner layers for VCC and GND. * Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are recommended.
DSP56362 Technical Data, Rev. 4 5-2 Freescale Semiconductor
Power Consumption Considerations
*
* * * * *
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the pins with internal pull-up resistors (TRST, TMS, DE, TCK, and TDI). Take special care to minimize noise levels on the VCCP, GNDP, and GNDP1 pins. If multiple DSP56362 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied before deassertion of RESET. At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip VCC never exceeds 3.95 V.
5.3
Power Consumption Considerations
Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the following formula: I = CxVxf where: C V f = node/pin capacitance = voltage swing = frequency of node/pin toggle
Example 1. Current Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock, toggling at its maximum possible rate (50 MHz), the current consumption is
I = 50 x 10
- 12
x 3.3 x 50 x 10 = 8.25mA
6
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption, do the following: * Set the EBD bit when not accessing external memory. * Minimize external memory accesses and use internal memory accesses. * Minimize the number of pins that are switching. * Minimize the capacitive load on the pins. * Connect the unused inputs to pull-up or pull-down resistors.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 5-3
PLL Performance Issues
* *
Disable unused peripherals. Disable unused pin activity (e.g., CLKOUT, XTAL).
One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value. 1MIPS = 1MHz = ( I typF2 - I typF1 ) x ( F2 - F1 ) where : ItypF2 = current at F2 ItypF1 = current at F1 F2 F1 = high frequency (any specified operating frequency) = low frequency (any specified operating frequency lower than F2) NOTE F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application.
5.4
PLL Performance Issues
The following explanations should be considered as general observations on expected PLL behavior. There is no testing that verifies these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges.
5.4.1
Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature, and voltage ranges. As defined in Figure 3-1, for input frequencies greater than 15 MHz and the MF 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between -1.4 ns and +3.2 ns.
5.4.2
Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than 2 ns.
DSP56362 Technical Data, Rev. 4 5-4 Freescale Semiconductor
Host Port Considerations
5.4.3
Frequency Jitter Performance
The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between 0.5% and approximately 2%. For large MF (MF > 500), the frequency jitter is 2-3%.
5.4.4
Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values.
5.5
Host Port Considerations
Careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. This synchronization is a common problem when two asynchronous systems are connected, as they are in the host interface. The following paragraphs present considerations for proper operation.
5.5.1
*
Host Programming Considerations
Unsynchronized Reading of Receive Byte Registers--When reading the receive byte registers, receive register high (RXH), receive register middle (RXM), or receive register low (RXL), the host interface programmer should use interrupts or poll the receive register data full (RXDF) flag that indicates whether data is available. This ensures that the data in the receive byte registers will be valid. Overwriting Transmit Byte Registers--The host interface programmer should not write to the transmit byte registers, transmit register high (TXH), transmit register middle (TXM), or transmit register low (TXL), unless the transmit register data empty (TXDE) bit is set, indicating that the transmit byte registers are empty. This ensures that the transmit byte registers will transfer valid data to the host receive (HRX) register. Synchronization of Status Bits from DSP to Host--HC, HOREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor (refer to the user's manual for descriptions of these status bits). The host can read these status bits very quickly without regard to the clock rate used by the DSP, but the state of the bit could be changing during the read operation. This is not generally a system problem, because the bit will be read correctly in the next pass of any host polling routine. However, if the host asserts HEN for more than timing number 31, with a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has
*
*
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 5-5
Host Port Considerations
*
*
*
significance, the host could read the wrong combination. Therefore, read the bits twice and check for consensus. Overwriting the Host Vector--The host interface programmer should change the host vector (HV) register only when the host command (HC) bit is clear. This ensures that the DSP interrupt control logic will receive a stable vector. Cancelling a Pending Host Command Exception--The host processor may elect to clear the HC bit to cancel the host command exception request at any time before it is recognized by the DSP. Because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the host command exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time that the HC bit is cleared. Variance in the Host Interface Timing--The host interface (HDI) may vary (e.g. due to the PLL lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together with the INIT and then polling INIT, ISR, and the HOREQ pin).
5.5.2
*
DSP Programming Considerations
Synchronization of Status Bits from Host to DSP--DMA, HF1, HF0, HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. (Refer to the user's manual for descriptions of these status bits.) Reading HF0 and HF1 as an Encoded Pair--Care must be exercised when reading status bits HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.
*
DSP56362 Technical Data, Rev. 4 5-6 Freescale Semiconductor
6
Ordering Information
Consult a Freescale Semiconductor, Inc. sales office or authorized distributor to determine product availability and to place an order. For information on ordering this and all DSP Audio products, review the SG1004 selector guide at http://www.freescale.com.
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 6-1
NOTES
DSP56362 Technical Data, Rev. 4 6-2 Freescale Semiconductor
Appendix A Power Consumption Benchmark
The following benchmark program permits evaluation of DSP power usage in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation.
;********************************************************************;********* *********************************************************** ;* ;* CHECKS Typical Power Consumption
;******************************************************************** page 200,55,0,0,0 nolist I_VEC EQU START EQU INT_PROG INT_XDAT INT_YDAT $000000 $8000 EQU $100 EQU $0 EQU $0 ; ; ; ; ; Interrupt vectors for program debug only MAIN (external) program starting address INTERNAL program memory starting address INTERNAL X-data memory starting address INTERNAL Y-data memory starting address
INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org ; movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM) ; Default: 1 w.s (SRAM) ; movep #$0d0000,x:M_PCTL ; XTAL disable ; PLL enable ; CLKOUT disable ; ; Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1 P:START
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor A-1
do move move XLOAD_LOOP ; ; Load the Y-data ; move move do move move YLOAD_LOOP ; jmp PROG_START move move move move ; clr clr move move move move bset ; sbr dor mac mac add mac mac move _end bra nop nop nop nop PROG_END nop nop
#(XDAT_END-XDAT_START),XLOAD_LOOP p:(r1)+,x0 x0,x:(r0)+
#INT_YDAT,r0 #YDAT_START,r1 #(YDAT_END-YDAT_START),YLOAD_LOOP p:(r1)+,x0 x0,y:(r0)+
INT_PROG
#$0,r0 #$0,r4 #$3f,m0 #$3f,m4 a b #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr
; ebd
#60,_end x0,y0,a x:(r0)+,x1 x1,y1,a x:(r0)+,x0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a b1,x:$ff sbr
y:(r4)+,y1 y:(r4)+,y0
y:(r4)+,y0
XDAT_START ; org dc dc dc dc
x:0 $262EB9 $86F2FE $E56A5F $616CAC
DSP56362 Technical Data, Rev. 4
A-2
Freescale Semiconductor
dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc
$8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E $CFFB2F $40753C $8262C5 $CA641A $EB3B4B $2DA928 $AB6641 $28A7E6 $4E2127
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
A-3
dc dc dc dc dc XDAT_END YDAT_START ; org dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc
$482FD4 $7257D $E53C72 $1A8C3 $E27540
y:0 $5B6DA $C3F70B $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 $A43E00 $C2B639 $85A47E $ABFDDF $F3A2C $2D7CF5 $E16A8A $ECB8FB $4BED18 $43F371 $83A556 $E1E9D7 $ACA2C4 $8135AD $2CE0E2 $8F2C73 $432730 $A87FA9 $4A292E $A63CCF $6BA65C $E06D65 $1AA3A $A1B6EB $48AC48 $EF7AE1 $6E3006 $62F6C7 $6064F4 $87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF
DSP56362 Technical Data, Rev. 4
A-4
Freescale Semiconductor
dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc YDAT_END
$4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor A-5
NOTES
DSP56362 Technical Data, Rev. 4 A-6 Freescale Semiconductor
Appendix B IBIS Model
[IBIS ver] 2.1 [File name] 56362.ibs [File Rev] 0.0 [Date] 29/6/2000 [Component] 56362 [Manufacturer] Freescale [Package] |variable typ R_pkg 45m L_pkg 2.5nH C_pkg 1.3pF
min 22m 1.1nH 1.2pF
max 75m 4.3nH 1.4pF
[Pin]signal_name model_name 1 sck ip5b_io 2 ss_ ip5b_io 3 hreq_ ip5b_io 4 sdo0 ip5b_io 5 sdo1 ip5b_io 6 sdoi23 ip5b_io 7 sdoi32 ip5b_io 8 svcc power 9 sgnd gnd 10 sdoi41 ip5b_io 11 sdoi50 ip5b_io 12 fst ip5b_io 13 fsr ip5b_io 14 sckt ip5b_io 15 sckr ip5b_io 16 hsckt ip5b_io 17 hsckr ip5b_io 18 qvccl power 19 gnd gnd 20 qvcch power 21 hp12 ip5b_io 22 hp11 ip5b_io 23 hp15 ip5b_io 24 hp14 ip5b_io 25 svcc power 26 sgnd gnd 27 ado ip5b_io 28 aci ip5b_io 29 tio ip5b_io 30 hp13 ip5b_io 31 hp10 ip5b_io 32 hp9 ip5b_io
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-1
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
hp8 hp7 hp6 hp5 hp4 svcc sgnd hp3 hp2 hp1 hp0 ires_ pvcc pcap pgnd pgnd1 qvcch aa3 aa2 cas_ de_ qgnd cxtldis_ qvccl cvcc cgnd clkout nmi_ ta_ br_ bb_ cvcc cgnd wr_ rd_ aa1 aa0 bg_ eab0 eab1 avcc agnd eab2 eab3 eab4 eab5 avcc agnd eab6 eab7 eab8 eab9 avcc agnd eab10
ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io power gnd ip5b_io ip5b_io ip5b_io ip5b_io ip5b_i power power gnd gnd power icbc_o icbc_o icbc_o ipbw_io gnd iexlh_i power power gnd icba_o ipbw_i icbc_o icbc_o icbc_o power gnd icbc_o icbc_o icbc_o icbc_o icbc_o icba_o icba_o power gnd icba_o icba_o icba_o icba_o power gnd icba_o icba_o icba_o icba_o power gnd icba_o
DSP56362 Technical Data, Rev. 4
B-2
Freescale Semiconductor
89 eab11 90 qgnd 91 qvcc 92 eab12 93 eab13 94 eab14 95 qvcch 96 agnd 97 eab15 98 eab16 99 eab17 100 edb0 101 edb1 102 edb2 103 dvcc 104 dgnd 105 edb3 106 edb4 107 edb5 108 edb6 109 edb7 110 edb8 111 dvcc 112 dgnd 113 edb9 114 edb10 115 edb11 116 edb12 117 edb13 118 edb14 119 dvcc 120 dgnd 121 edb15 122 edb16 123 edb17 124 edb18 125 edb19 126 qvccl 127 qgnd 128 edb20 129 dvcc 130 dgnd 131 edb21 132 edb22 133 edb23 134 irqd_ 135 irqc_ 136 irqb_ 137 irqa_ 138 trst_ 139 tdo 140 tdi 141 tck 142 tms 143 mosi
icba_o gnd power icba_o icba_o icba_o power gnd icba_o icba_o icba_o icba_io icba_io icba_io power gnd icba_io icba_io icba_io icba_io icba_io icba_io power gnd icba_io icba_io icba_io icba_io icba_io icba_io power gnd icba_io icba_io icba_io icba_io icba_io power gnd icba_io power gnd icba_io icba_io icba_io ip5b_i ip5b_i ip5b_i ip5b_i ip5b_i ip5b_o ip5b_i ip5b_i ip5b_i ip5b_io
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
B-3
144 sda ip5b_io | [Model] ip5b_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | | [Model] ip5b_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02
DSP56362 Technical Data, Rev. 4 B-4 Freescale Semiconductor
-1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00
-7.83e+01 -4.43e+01 -1.02e+01 -5.10e-02 -3.65e-02 -2.65e-02 -1.62e-02 -5.49e-03 5.377e-03 1.516e-02 2.370e-02 3.098e-02 3.700e-02 4.175e-02 4.531e-02 4.779e-02 4.935e-02 5.013e-02 5.046e-02 5.063e-02 5.075e-02 5.085e-02 5.090e-02 4.771e-02 4.525e-02 4.657e-02 4.904e-02 5.221e-02 5.524e-02 5.634e-02 5.751e-02 5.634e-02 5.648e-02 5.664e-02 5.679e-02 5.693e-02 5.707e-02 5.722e-02 5.741e-02 5.766e-02 5.801e-02 5.824e-02
-6.88e+01 -4.52e+01 -2.15e+01 -1.18e+00 -2.25e-02 -1.38e-02 -8.35e-03 -2.80e-03 2.744e-03 7.871e-03 1.252e-02 1.667e-02 2.026e-02 2.324e-02 2.553e-02 2.709e-02 2.803e-02 2.851e-02 2.876e-02 2.892e-02 2.904e-02 2.912e-02 2.876e-02 2.994e-02 3.321e-02 3.570e-02 3.801e-02 4.029e-02 4.253e-02 4.463e-02 4.645e-02 4.786e-02 4.881e-02 4.912e-02 4.795e-02 4.679e-02 4.688e-02 4.700e-02 4.712e-02 4.723e-02 4.733e-02 4.737e-02
-7.58e+01 -4.17e+01 -7.69e+00 -5.63e-02 -4.28e-02 -3.12e-02 -1.91e-02 -6.52e-03 6.427e-03 1.823e-02 2.869e-02 3.776e-02 4.544e-02 5.171e-02 5.660e-02 6.023e-02 6.271e-02 6.419e-02 6.494e-02 6.525e-02 6.540e-02 6.549e-02 6.555e-02 6.561e-02 6.182e-02 6.049e-02 6.178e-02 6.450e-02 6.659e-02 6.867e-02 6.970e-02 6.938e-02 6.960e-02 6.983e-02 7.005e-02 7.026e-02 7.049e-02 7.074e-02 7.105e-02 7.147e-02 7.205e-02 7.242e-02
I(typ) 2.922e-04 2.881e-04 2.853e-04 2.836e-04 2.825e-04 2.819e-04 2.815e-04 2.813e-04 2.812e-04
I(min) 2.177e-04 2.175e-04 2.173e-04 2.172e-04 2.171e-04 2.170e-04 2.169e-04 2.167e-04 2.520e-04
I(max) 4.123e-04 4.021e-04 3.946e-04 3.893e-04 3.857e-04 3.834e-04 3.820e-04 3.812e-04 3.808e-04
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-5
-1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00
2.811e-04 2.810e-04 2.809e-04 2.808e-04 2.997e-04 1.750e-02 1.048e-02 3.487e-03 -3.40e-03 -9.69e-03 -1.52e-02 -2.02e-02 -2.46e-02 -2.84e-02 -3.14e-02 -3.37e-02 -3.55e-02 -3.68e-02 -3.78e-02 -3.85e-02 -3.91e-02 -3.96e-02 -4.01e-02 -4.04e-02 -4.08e-02 -4.11e-02 -4.14e-02 -4.17e-02 -4.32e-02 -4.08e-01 -2.73e+01 -6.13e+01 -9.54e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02
3.078e-02 2.684e-02 2.277e-02 1.864e-02 1.447e-02 1.031e-02 6.181e-03 2.084e-03 -2.03e-03 -5.71e-03 -8.99e-03 -1.19e-02 -1.43e-02 -1.62e-02 -1.77e-02 -1.88e-02 -1.95e-02 -2.00e-02 -2.04e-02 -2.07e-02 -2.10e-02 -2.12e-02 -2.15e-02 -2.17e-02 -2.18e-02 -2.20e-02 -2.78e-02 -1.20e+00 -2.15e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02
3.806e-04 3.804e-04 3.802e-04 3.801e-04 3.799e-04 3.797e-04 3.776e-04 4.568e-03 -4.22e-03 -1.24e-02 -1.95e-02 -2.61e-02 -3.21e-02 -3.73e-02 -4.18e-02 -4.55e-02 -4.85e-02 -5.09e-02 -5.27e-02 -5.41e-02 -5.51e-02 -5.60e-02 -5.67e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -5.94e-02 -5.98e-02 -6.10e-02 -6.84e-02 -7.73e+00 -4.18e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02
I(typ) -5.21e+02 -4.69e+02 -4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01
I(max) -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.61e+02 -1.10e+02
DSP56362 Technical Data, Rev. 4 B-6 Freescale Semiconductor
-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dV/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | | [Model] ip5b_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.69e+00 -9.00e-01 -5.10e-02 -1.18e+00 -5.63e-02 -7.00e-01 -3.65e-02 -2.25e-02 -4.28e-02 -5.00e-01 -2.65e-02 -1.38e-02 -3.12e-02 -3.00e-01 -1.62e-02 -8.35e-03 -1.91e-02 -1.00e-01 -5.49e-03 -2.80e-03 -6.52e-03 1.000e-01 5.377e-03 2.744e-03 6.427e-03 3.000e-01 1.516e-02 7.871e-03 1.823e-02 5.000e-01 2.370e-02 1.252e-02 2.869e-02 7.000e-01 3.098e-02 1.667e-02 3.776e-02 9.000e-01 3.700e-02 2.026e-02 4.544e-02 1.100e+00 4.175e-02 2.324e-02 5.171e-02 1.300e+00 4.531e-02 2.553e-02 5.660e-02
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-7
1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00
4.779e-02 4.935e-02 5.013e-02 5.046e-02 5.063e-02 5.075e-02 5.085e-02 5.090e-02 4.771e-02 4.525e-02 4.657e-02 4.904e-02 5.221e-02 5.524e-02 5.634e-02 5.751e-02 5.634e-02 5.648e-02 5.664e-02 5.679e-02 5.693e-02 5.707e-02 5.722e-02 5.741e-02 5.766e-02 5.801e-02 5.824e-02
2.709e-02 2.803e-02 2.851e-02 2.876e-02 2.892e-02 2.904e-02 2.912e-02 2.876e-02 2.994e-02 3.321e-02 3.570e-02 3.801e-02 4.029e-02 4.253e-02 4.463e-02 4.645e-02 4.786e-02 4.881e-02 4.912e-02 4.795e-02 4.679e-02 4.688e-02 4.700e-02 4.712e-02 4.723e-02 4.733e-02 4.737e-02
6.023e-02 6.271e-02 6.419e-02 6.494e-02 6.525e-02 6.540e-02 6.549e-02 6.555e-02 6.561e-02 6.182e-02 6.049e-02 6.178e-02 6.450e-02 6.659e-02 6.867e-02 6.970e-02 6.938e-02 6.960e-02 6.983e-02 7.005e-02 7.026e-02 7.049e-02 7.074e-02 7.105e-02 7.147e-02 7.205e-02 7.242e-02
I(typ) 2.922e-04 2.881e-04 2.853e-04 2.836e-04 2.825e-04 2.819e-04 2.815e-04 2.813e-04 2.812e-04 2.811e-04 2.810e-04 2.809e-04 2.808e-04 2.997e-04 1.750e-02 1.048e-02 3.487e-03 -3.40e-03 -9.69e-03 -1.52e-02 -2.02e-02 -2.46e-02 -2.84e-02 -3.14e-02
I(min) 2.177e-04 2.175e-04 2.173e-04 2.172e-04 2.171e-04 2.170e-04 2.169e-04 2.167e-04 2.520e-04 3.078e-02 2.684e-02 2.277e-02 1.864e-02 1.447e-02 1.031e-02 6.181e-03 2.084e-03 -2.03e-03 -5.71e-03 -8.99e-03 -1.19e-02 -1.43e-02 -1.62e-02 -1.77e-02
I(max) 4.123e-04 4.021e-04 3.946e-04 3.893e-04 3.857e-04 3.834e-04 3.820e-04 3.812e-04 3.808e-04 3.806e-04 3.804e-04 3.802e-04 3.801e-04 3.799e-04 3.797e-04 3.776e-04 4.568e-03 -4.22e-03 -1.24e-02 -1.95e-02 -2.61e-02 -3.21e-02 -3.73e-02 -4.18e-02
DSP56362 Technical Data, Rev. 4 B-8 Freescale Semiconductor
1.500e+00 -3.37e-02 1.700e+00 -3.55e-02 1.900e+00 -3.68e-02 2.100e+00 -3.78e-02 2.300e+00 -3.85e-02 2.500e+00 -3.91e-02 2.700e+00 -3.96e-02 2.900e+00 -4.01e-02 3.100e+00 -4.04e-02 3.300e+00 -4.08e-02 3.500e+00 -4.11e-02 3.700e+00 -4.14e-02 3.900e+00 -4.17e-02 4.100e+00 -4.32e-02 4.300e+00 -4.08e-01 4.500e+00 -2.73e+01 4.700e+00 -6.13e+01 4.900e+00 -9.54e+01 5.100e+00 -1.38e+02 5.300e+00 -1.89e+02 5.500e+00 -2.40e+02 5.700e+00 -2.91e+02 5.900e+00 -3.42e+02 6.100e+00 -3.93e+02 6.300e+00 -4.44e+02 6.500e+00 -4.95e+02 6.600e+00 -5.21e+02 | [GND_clamp] |voltage I(typ) | -3.30e+00 -5.21e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 -2.14e+02 -1.90e+00 -1.63e+02 -1.70e+00 -1.13e+02 -1.50e+00 -7.83e+01 -1.30e+00 -4.43e+01 -1.10e+00 -1.02e+01 -9.00e-01 -9.69e-03 -7.00e-01 -2.83e-04 -5.00e-01 -1.35e-06 -3.00e-01 -1.31e-09 -1.00e-01 -2.92e-11 0.000e+00 -2.44e-11 | [Ramp] R_load = 50.00 |voltage I(typ) | |
-1.88e-02 -1.95e-02 -2.00e-02 -2.04e-02 -2.07e-02 -2.10e-02 -2.12e-02 -2.15e-02 -2.17e-02 -2.18e-02 -2.20e-02 -2.78e-02 -1.20e+00 -2.15e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02
-4.55e-02 -4.85e-02 -5.09e-02 -5.27e-02 -5.41e-02 -5.51e-02 -5.60e-02 -5.67e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -5.94e-02 -5.98e-02 -6.10e-02 -6.84e-02 -7.73e+00 -4.18e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.18e+00 -5.70e-03 -4.53e-05 -3.74e-07 -3.00e-09 -5.14e-10
I(max) -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.61e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.67e+00 -7.81e-03 -8.42e-04 -1.00e-05 -8.58e-09 -3.64e-11 -2.79e-11
I(min)
I(max)
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-9
dV/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dV/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | | [Model] icba_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00 -9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02 -7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02 -5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 1.299e-01 6.458e-02 2.331e-02 1.700e+00 1.366e-01 6.746e-02 1.755e-01 1.900e+00 1.404e-01 6.916e-02 1.847e-01 2.100e+00 1.423e-01 7.006e-02 1.907e-01 2.300e+00 1.433e-01 7.059e-02 1.940e-01 2.500e+00 1.440e-01 7.098e-02 1.958e-01 2.700e+00 1.445e-01 7.128e-02 1.970e-01 2.900e+00 1.450e-01 7.154e-02 1.979e-01 3.100e+00 1.454e-01 7.176e-02 1.986e-01 3.300e+00 1.458e-01 7.196e-02 1.993e-01 3.500e+00 1.461e-01 7.223e-02 1.999e-01 3.700e+00 1.464e-01 8.810e-02 2.004e-01 3.900e+00 1.469e-01 2.589e+00 2.009e-01
DSP56362 Technical Data, Rev. 4 B-10 Freescale Semiconductor
4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00
1.490e-01 1.501e+00 1.813e+01 3.540e+01 5.269e+01 7.541e+01 1.012e+02 1.270e+02 1.527e+02 1.785e+02 2.043e+02 2.301e+02 2.559e+02 2.688e+02
1.451e+01 2.658e+01 3.866e+01 5.076e+01 6.461e+01 8.261e+01 1.006e+02 1.186e+02 1.366e+02 1.546e+02 1.726e+02 1.906e+02 2.086e+02 2.176e+02
2.015e-01 2.030e-01 2.385e-01 9.563e+00 2.682e+01 4.409e+01 6.258e+01 8.836e+01 1.141e+02 1.399e+02 1.657e+02 1.915e+02 2.173e+02 2.302e+02
I(typ) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.360e+00 4.275e-02 8.208e-03 5.635e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -1.25e-01 -1.31e-01 -1.36e-01 -1.40e-01 -1.42e-01 -1.44e-01 -1.46e-01 -1.48e-01 -1.49e-01 -1.50e-01 -1.52e-01 -1.53e-01 -1.54e-01
I(min) 1.905e+02 1.725e+02 1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01 5.068e+01 3.859e+01 2.651e+01 1.444e+01 2.518e+00 2.012e-02 3.518e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -6.55e-02 -6.93e-02 -7.19e-02 -7.38e-02 -7.53e-02 -7.65e-02 -7.76e-02 -7.85e-02 -7.93e-02 -8.00e-02 -8.06e-02 -8.13e-02 -8.84e-02 -1.26e+00
I(max) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.362e+00 4.663e-02 1.070e-02 7.068e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.38e-02 -1.70e-01 -1.82e-01 -1.91e-01 -1.97e-01 -2.03e-01 -2.07e-01 -2.10e-01 -2.13e-01 -2.15e-01 -2.17e-01 -2.19e-01 -2.21e-01 -2.22e-01
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-11
4.100e+00 -1.57e-01 4.300e+00 -5.25e-01 4.500e+00 -2.74e+01 4.700e+00 -6.14e+01 4.900e+00 -9.55e+01 5.100e+00 -1.38e+02 5.300e+00 -1.89e+02 5.500e+00 -2.40e+02 5.700e+00 -2.91e+02 5.900e+00 -3.42e+02 6.100e+00 -3.93e+02 6.300e+00 -4.44e+02 6.500e+00 -4.95e+02 6.600e+00 -5.21e+02 | [GND_clamp] |voltage I(typ) | -3.30e+00 -5.20e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 -2.14e+02 -1.90e+00 -1.63e+02 -1.70e+00 -1.13e+02 -1.50e+00 -7.83e+01 -1.30e+00 -4.43e+01 -1.10e+00 -1.02e+01 -9.00e-01 -1.22e-02 -7.00e-01 -5.18e-04 -5.00e-01 -2.43e-06 -3.00e-01 -2.33e-09 -1.00e-01 -2.10e-11 0.000e+00 -1.70e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.686e+02 -3.10e+00 2.428e+02 -2.90e+00 2.170e+02 -2.70e+00 1.912e+02 -2.50e+00 1.655e+02 -2.30e+00 1.397e+02 -2.10e+00 1.139e+02 -1.90e+00 8.814e+01 -1.70e+00 6.236e+01 -1.50e+00 4.389e+01 -1.30e+00 2.662e+01 -1.10e+00 9.358e+00 -9.00e-01 3.399e-02 -7.00e-01 3.426e-04 -5.00e-01 2.840e-06
-2.16e+01 -4.53e+01 -6.89e+01 -9.26e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.19e+02
-2.24e-01 -2.27e-01 -2.38e-01 -7.90e+00 -4.20e+01 -7.60e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.42e+02
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.18e+00 -6.62e-03 -6.64e-05 -6.35e-07 -6.31e-09 -1.95e-09
I(max) -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.67e+00 -1.17e-02 -1.56e-03 -1.80e-05 -1.54e-08 -2.99e-11 -1.91e-11
I(min) 1.905e+02 1.725e+02 1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01 5.068e+01 3.859e+01 2.651e+01 1.444e+01 2.517e+00 1.577e-02 7.857e-05
I(max) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.359e+00 3.554e-02 9.211e-04 1.655e-05
DSP56362 Technical Data, Rev. 4 B-12 Freescale Semiconductor
-3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dV/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | | [Model] icba_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00 -9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02 -7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02 -5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 1.299e-01 6.458e-02 2.331e-02 1.700e+00 1.366e-01 6.746e-02 1.755e-01 1.900e+00 1.404e-01 6.916e-02 1.847e-01 2.100e+00 1.423e-01 7.006e-02 1.907e-01 2.300e+00 1.433e-01 7.059e-02 1.940e-01 2.500e+00 1.440e-01 7.098e-02 1.958e-01
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-13
2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00
1.445e-01 1.450e-01 1.454e-01 1.458e-01 1.461e-01 1.464e-01 1.469e-01 1.490e-01 1.501e+00 1.813e+01 3.540e+01 5.269e+01 7.541e+01 1.012e+02 1.270e+02 1.527e+02 1.785e+02 2.043e+02 2.301e+02 2.559e+02 2.688e+02
7.128e-02 7.154e-02 7.176e-02 7.196e-02 7.223e-02 8.810e-02 2.589e+00 1.451e+01 2.658e+01 3.866e+01 5.076e+01 6.461e+01 8.261e+01 1.006e+02 1.186e+02 1.366e+02 1.546e+02 1.726e+02 1.906e+02 2.086e+02 2.176e+02
1.970e-01 1.979e-01 1.986e-01 1.993e-01 1.999e-01 2.004e-01 2.009e-01 2.015e-01 2.030e-01 2.385e-01 9.563e+00 2.682e+01 4.409e+01 6.258e+01 8.836e+01 1.141e+02 1.399e+02 1.657e+02 1.915e+02 2.173e+02 2.302e+02
I(typ) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.360e+00 4.275e-02 8.208e-03 5.635e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -1.25e-01 -1.31e-01 -1.36e-01 -1.40e-01 -1.42e-01 -1.44e-01
I(min) 1.905e+02 1.725e+02 1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01 5.068e+01 3.859e+01 2.651e+01 1.444e+01 2.518e+00 2.012e-02 3.518e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -6.55e-02 -6.93e-02 -7.19e-02 -7.38e-02 -7.53e-02 -7.65e-02 -7.76e-02
I(max) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.362e+00 4.663e-02 1.070e-02 7.068e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.38e-02 -1.70e-01 -1.82e-01 -1.91e-01 -1.97e-01 -2.03e-01 -2.07e-01
DSP56362 Technical Data, Rev. 4 B-14 Freescale Semiconductor
2.700e+00 -1.46e-01 2.900e+00 -1.48e-01 3.100e+00 -1.49e-01 3.300e+00 -1.50e-01 3.500e+00 -1.52e-01 3.700e+00 -1.53e-01 3.900e+00 -1.54e-01 4.100e+00 -1.57e-01 4.300e+00 -5.25e-01 4.500e+00 -2.74e+01 4.700e+00 -6.14e+01 4.900e+00 -9.55e+01 5.100e+00 -1.38e+02 5.300e+00 -1.89e+02 5.500e+00 -2.40e+02 5.700e+00 -2.91e+02 5.900e+00 -3.42e+02 6.100e+00 -3.93e+02 6.300e+00 -4.44e+02 6.500e+00 -4.95e+02 6.600e+00 -5.21e+02 | [GND_clamp] |voltage I(typ) | -3.30e+00 -5.20e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 -2.14e+02 -1.90e+00 -1.63e+02 -1.70e+00 -1.13e+02 -1.50e+00 -7.83e+01 -1.30e+00 -4.43e+01 -1.10e+00 -1.02e+01 -9.00e-01 -1.22e-02 -7.00e-01 -5.18e-04 -5.00e-01 -2.43e-06 -3.00e-01 -2.33e-09 -1.00e-01 -2.10e-11 0.000e+00 -1.70e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.686e+02 -3.10e+00 2.428e+02 -2.90e+00 2.170e+02 -2.70e+00 1.912e+02 -2.50e+00 1.655e+02 -2.30e+00 1.397e+02 -2.10e+00 1.139e+02 -1.90e+00 8.814e+01
-7.85e-02 -7.93e-02 -8.00e-02 -8.06e-02 -8.13e-02 -8.84e-02 -1.26e+00 -2.16e+01 -4.53e+01 -6.89e+01 -9.26e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.19e+02
-2.10e-01 -2.13e-01 -2.15e-01 -2.17e-01 -2.19e-01 -2.21e-01 -2.22e-01 -2.24e-01 -2.27e-01 -2.38e-01 -7.90e+00 -4.20e+01 -7.60e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.42e+02
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.18e+00 -6.62e-03 -6.64e-05 -6.35e-07 -6.31e-09 -1.95e-09
I(max) -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.67e+00 -1.17e-02 -1.56e-03 -1.80e-05 -1.54e-08 -2.99e-11 -1.91e-11
I(min) 1.905e+02 1.725e+02 1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01
I(max) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-15
-1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dV/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | | [Model] icbc_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -2.51e-02 -1.18e+00 -2.65e-02 -7.00e-01 -1.30e-02 -1.16e-02 -1.58e-02 -5.00e-01 -9.33e-03 -4.67e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02
DSP56362 Technical Data, Rev. 4 B-16 Freescale Semiconductor
1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00
1.688e-02 9.632e-02 1.012e-01 1.039e-01 1.053e-01 1.060e-01 1.065e-01 1.069e-01 1.073e-01 1.076e-01 1.078e-01 1.081e-01 1.083e-01 1.086e-01 1.103e-01 1.437e+00 1.800e+01 3.519e+01 5.241e+01 7.505e+01 1.007e+02 1.264e+02 1.522e+02 1.779e+02 2.036e+02 2.293e+02 2.550e+02 2.678e+02
8.240e-03 4.783e-02 4.994e-02 5.118e-02 5.184e-02 5.223e-02 5.251e-02 5.274e-02 5.293e-02 5.309e-02 5.324e-02 5.344e-02 6.705e-02 2.529e+00 1.438e+01 2.638e+01 3.839e+01 5.041e+01 6.419e+01 8.210e+01 1.000e+02 1.179e+02 1.359e+02 1.538e+02 1.717e+02 1.896e+02 2.075e+02 2.165e+02
2.162e-02 2.331e-02 1.302e-01 1.369e-01 1.412e-01 1.436e-01 1.449e-01 1.458e-01 1.464e-01 1.470e-01 1.475e-01 1.479e-01 1.483e-01 1.487e-01 1.491e-01 1.503e-01 1.810e-01 9.452e+00 2.664e+01 4.384e+01 6.224e+01 8.794e+01 1.136e+02 1.394e+02 1.651e+02 1.908e+02 2.165e+02 2.293e+02
I(typ) 2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.302e+00 3.838e-02 8.115e-03 5.634e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03
I(min) 1.896e+02 1.716e+02 1.537e+02 1.358e+02 1.179e+02 9.996e+01 8.205e+01 6.413e+01 5.035e+01 3.834e+01 2.633e+01 1.433e+01 2.477e+00 1.789e-02 3.503e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03
I(max) 2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.303e+00 4.183e-02 1.045e-02 7.064e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-17
1.300e+00 -1.03e-02 1.500e+00 -9.03e-02 1.700e+00 -9.49e-02 1.900e+00 -9.84e-02 2.100e+00 -1.01e-01 2.300e+00 -1.03e-01 2.500e+00 -1.05e-01 2.700e+00 -1.06e-01 2.900e+00 -1.07e-01 3.100e+00 -1.08e-01 3.300e+00 -1.09e-01 3.500e+00 -1.10e-01 3.700e+00 -1.11e-01 3.900e+00 -1.11e-01 4.100e+00 -1.14e-01 4.300e+00 -4.76e-01 4.500e+00 -2.73e+01 4.700e+00 -6.14e+01 4.900e+00 -9.54e+01 5.100e+00 -1.38e+02 5.300e+00 -1.89e+02 5.500e+00 -2.40e+02 5.700e+00 -2.91e+02 5.900e+00 -3.42e+02 6.100e+00 -3.93e+02 6.300e+00 -4.44e+02 6.500e+00 -4.95e+02 6.600e+00 -5.20e+02 | [GND_clamp] |voltage I(typ) | -3.30e+00 -5.20e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 -2.14e+02 -1.90e+00 -1.63e+02 -1.70e+00 -1.13e+02 -1.50e+00 -7.83e+01 -1.30e+00 -4.42e+01 -1.10e+00 -1.02e+01 -9.00e-01 -1.03e-02 -7.00e-01 -3.74e-04 -5.00e-01 -1.72e-06 -3.00e-01 -1.67e-09 -1.00e-01 -2.03e-11 0.000e+00 -1.69e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.677e+02
-4.75e-02 -5.02e-02 -5.21e-02 -5.34e-02 -5.45e-02 -5.54e-02 -5.62e-02 -5.68e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -6.49e-02 -1.23e+00 -2.16e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02
-1.41e-02 -1.23e-01 -1.31e-01 -1.38e-01 -1.43e-01 -1.47e-01 -1.50e-01 -1.52e-01 -1.54e-01 -1.56e-01 -1.57e-01 -1.59e-01 -1.60e-01 -1.61e-01 -1.62e-01 -1.64e-01 -1.73e-01 -7.82e+00 -4.19e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.51e+01 -2.15e+01 -1.17e+00 -5.73e-03 -5.06e-05 -4.65e-07 -4.80e-09 -1.61e-09
I(max) -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.11e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.66e+00 -9.27e-03 -1.14e-03 -1.28e-05 -1.10e-08 -2.71e-11 -1.89e-11
I(min) 1.896e+02
I(max) 2.677e+02
DSP56362 Technical Data, Rev. 4 B-18 Freescale Semiconductor
-3.10e+00 2.420e+02 1.716e+02 2.420e+02 -2.90e+00 2.163e+02 1.537e+02 2.163e+02 -2.70e+00 1.906e+02 1.358e+02 1.906e+02 -2.50e+00 1.649e+02 1.179e+02 1.649e+02 -2.30e+00 1.392e+02 9.996e+01 1.392e+02 -2.10e+00 1.135e+02 8.205e+01 1.135e+02 -1.90e+00 8.778e+01 6.413e+01 8.778e+01 -1.70e+00 6.208e+01 5.035e+01 6.208e+01 -1.50e+00 4.368e+01 3.834e+01 4.368e+01 -1.30e+00 2.649e+01 2.633e+01 2.649e+01 -1.10e+00 9.300e+00 1.433e+01 9.301e+00 -9.00e-01 2.962e-02 2.475e+00 3.075e-02 -7.00e-01 2.501e-04 1.354e-02 6.708e-04 -5.00e-01 2.066e-06 6.280e-05 1.204e-05 -3.00e-01 2.487e-09 5.128e-07 1.417e-08 -1.00e-01 5.672e-11 5.639e-09 6.832e-11 0.000e+00 5.334e-11 1.992e-09 5.783e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.570/0.200 1.210/0.411 1.810/0.149 | | dV/dt_f 1.590/0.304 1.170/0.673 1.800/0.205 | | [Model] ipbw_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00 -9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03 -7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-19
-5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06 -3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | | [Model] ipbw_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.66e+00 -9.00e-01 -3.69e-02 -1.17e+00 -3.79e-02 -7.00e-01 -2.52e-02 -1.67e-02 -2.81e-02 -5.00e-01 -1.83e-02 -9.77e-03 -2.04e-02
DSP56362 Technical Data, Rev. 4 B-20 Freescale Semiconductor
-3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01
-1.11e-02 -3.77e-03 3.729e-03 1.076e-02 1.723e-02 2.311e-02 2.836e-02 3.292e-02 3.675e-02 3.979e-02 4.205e-02 4.347e-02 4.413e-02 4.445e-02 4.465e-02 4.479e-02 4.492e-02 4.502e-02 4.511e-02 4.519e-02 4.526e-02 4.536e-02 4.614e-02 1.344e+00 1.783e+01 3.495e+01 5.208e+01 7.463e+01 1.002e+02 1.259e+02 1.515e+02 1.771e+02 2.027e+02 2.283e+02 2.539e+02 2.667e+02
-5.89e-03 -1.98e-03 1.940e-03 5.578e-03 8.907e-03 1.191e-02 1.455e-02 1.680e-02 1.862e-02 1.997e-02 2.085e-02 2.136e-02 2.162e-02 2.176e-02 2.186e-02 2.194e-02 2.200e-02 2.206e-02 2.211e-02 2.219e-02 3.324e-02 2.452e+00 1.423e+01 2.615e+01 3.808e+01 5.001e+01 6.371e+01 8.154e+01 9.937e+01 1.172e+02 1.350e+02 1.529e+02 1.707e+02 1.885e+02 2.064e+02 2.153e+02
-1.24e-02 -4.20e-03 4.177e-03 1.216e-02 1.965e-02 2.663e-02 3.305e-02 3.887e-02 4.404e-02 4.850e-02 5.223e-02 5.518e-02 5.728e-02 5.843e-02 5.899e-02 5.931e-02 5.953e-02 5.971e-02 5.986e-02 5.999e-02 6.010e-02 6.021e-02 6.032e-02 6.065e-02 8.548e-02 9.298e+00 2.640e+01 4.352e+01 6.184e+01 8.745e+01 1.131e+02 1.387e+02 1.643e+02 1.899e+02 2.155e+02 2.283e+02
I(typ) 2.667e+02 2.411e+02 2.155e+02 1.898e+02 1.642e+02 1.386e+02 1.130e+02 8.739e+01 6.178e+01 4.346e+01 2.635e+01 9.243e+00 5.536e-02 2.847e-02 2.025e-02
I(min) 1.885e+02 1.707e+02 1.528e+02 1.350e+02 1.172e+02 9.935e+01 8.152e+01 6.369e+01 4.999e+01 3.806e+01 2.613e+01 1.421e+01 2.435e+00 2.689e-02 1.265e-02
I(max) 2.667e+02 2.411e+02 2.155e+02 1.898e+02 1.642e+02 1.386e+02 1.130e+02 8.739e+01 6.178e+01 4.346e+01 2.635e+01 9.245e+00 6.260e-02 3.437e-02 2.451e-02
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-21
-3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01
1.208e-02 3.994e-03 -3.88e-03 -1.11e-02 -1.76e-02 -2.35e-02 -2.86e-02 -3.30e-02 -3.65e-02 -3.92e-02 -4.12e-02 -4.26e-02 -4.36e-02 -4.43e-02 -4.49e-02 -4.54e-02 -4.58e-02 -4.61e-02 -4.65e-02 -4.68e-02 -4.70e-02 -4.73e-02 -4.81e-02 -4.00e-01 -2.72e+01 -6.12e+01 -9.52e+01 -1.37e+02 -1.88e+02 -2.39e+02 -2.90e+02 -3.41e+02 -3.92e+02 -4.43e+02 -4.94e+02 -5.20e+02
7.503e-03 2.474e-03 -2.38e-03 -6.76e-03 -1.06e-02 -1.40e-02 -1.69e-02 -1.93e-02 -2.10e-02 -2.22e-02 -2.29e-02 -2.35e-02 -2.38e-02 -2.42e-02 -2.44e-02 -2.47e-02 -2.49e-02 -2.50e-02 -2.52e-02 -2.54e-02 -2.99e-02 -1.19e+00 -2.15e+01 -4.51e+01 -6.87e+01 -9.24e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.58e+02 -2.94e+02 -3.29e+02 -3.65e+02 -4.00e+02 -4.18e+02
1.467e-02 4.868e-03 -4.76e-03 -1.37e-02 -2.20e-02 -2.95e-02 -3.63e-02 -4.23e-02 -4.75e-02 -5.17e-02 -5.51e-02 -5.77e-02 -5.97e-02 -6.11e-02 -6.22e-02 -6.31e-02 -6.38e-02 -6.44e-02 -6.49e-02 -6.54e-02 -6.58e-02 -6.62e-02 -6.66e-02 -6.72e-02 -7.21e-02 -7.70e+00 -4.17e+01 -7.57e+01 -1.10e+02 -1.60e+02 -2.11e+02 -2.62e+02 -3.13e+02 -3.64e+02 -4.15e+02 -4.41e+02
I(typ) -5.20e+02 -4.69e+02 -4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.82e+01 -4.42e+01 -1.02e+01 -7.17e-03 -1.14e-04 -4.86e-07
I(min) -3.65e+02 -3.29e+02 -2.94e+02 -2.58e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.24e+01 -6.87e+01 -4.51e+01 -2.15e+01 -1.16e+00 -4.39e-03 -2.55e-05
I(max) -5.17e+02 -4.66e+02 -4.15e+02 -3.64e+02 -3.13e+02 -2.62e+02 -2.11e+02 -1.60e+02 -1.10e+02 -7.57e+01 -4.16e+01 -7.64e+00 -4.87e-03 -3.03e-04 -2.73e-06
DSP56362 Technical Data, Rev. 4 B-22 Freescale Semiconductor
-3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.140/0.494 0.699/0.978 1.400/0.354 | | dV/dt_f 1.150/0.505 0.642/0.956 1.350/0.350 | | [Model] iexlh_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.66e+02 -5.18e+02 -3.10e+00 -4.70e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.19e+02 -2.95e+02 -4.16e+02 -2.70e+00 -3.68e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.17e+02 -2.24e+02 -3.14e+02 -2.30e+00 -2.66e+02 -1.89e+02 -2.63e+02
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor B-23
-2.10e+00 -2.15e+02 -1.90e+00 -1.64e+02 -1.70e+00 -1.14e+02 -1.50e+00 -7.93e+01 -1.30e+00 -4.53e+01 -1.10e+00 -1.13e+01 -9.00e-01 -7.94e-03 -7.00e-01 -1.62e-06 -5.00e-01 -3.45e-10 -3.00e-01 -1.29e-11 -1.00e-01 -1.10e-11 0.000e+00 -1.01e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.653e+02 -3.10e+00 2.398e+02 -2.90e+00 2.143e+02 -2.70e+00 1.888e+02 -2.50e+00 1.633e+02 -2.30e+00 1.378e+02 -2.10e+00 1.123e+02 -1.90e+00 8.682e+01 -1.70e+00 6.133e+01 -1.50e+00 4.313e+01 -1.30e+00 2.614e+01 -1.10e+00 9.145e+00 -9.00e-01 1.797e-02 -7.00e-01 3.667e-06 -5.00e-01 7.730e-10 -3.00e-01 2.293e-11 -1.00e-01 2.096e-11 0.000e+00 2.004e-11 | [End]
-1.53e+02 -1.18e+02 -9.34e+01 -6.98e+01 -4.62e+01 -2.26e+01 -1.87e+00 -5.11e-03 -1.40e-05 -3.90e-08 -8.67e-10 -7.13e-10
-2.12e+02 -1.61e+02 -1.11e+02 -7.68e+01 -4.28e+01 -8.78e+00 -3.77e-03 -7.69e-07 -1.72e-10 -1.38e-11 -1.19e-11 -1.10e-11
I(min) 1.870e+02 1.693e+02 1.516e+02 1.339e+02 1.162e+02 9.847e+01 8.076e+01 6.305e+01 4.947e+01 3.766e+01 2.585e+01 1.404e+01 2.364e+00 7.589e-03 2.072e-05 5.767e-08 1.163e-09 9.618e-10
I(max) 2.653e+02 2.398e+02 2.143e+02 1.888e+02 1.633e+02 1.378e+02 1.123e+02 8.682e+01 6.133e+01 4.313e+01 2.614e+01 9.145e+00 1.797e-02 3.667e-06 7.748e-10 2.476e-11 2.278e-11 2.186e-11
DSP56362 Technical Data, Rev. 4 B-24 Freescale Semiconductor
Index
A
ac electrical characteristics 3 Address Trace mode 3, 38, 41 applications 5 arbitration bus timings 41 electrical 3 PLL 4, 5 power consumption 3 thermal 1 Digital Audio Transmitter 4, 16 DRAM out of page read access 36 wait states selection guide 28 write access 37 out of page and refresh timings 11 wait states 32 15 wait states 33 4 wait states 28 8 wait states 30 Page mode read accesses 27 wait states selection guide 19 write accesses 26 Page mode timings 1 wait state 19 2 wait states 21 3 wait states 22 4 wait states 24 refresh access 38 DRAM controller 4 DSP programming 6
B
bootstrap ROM 3 Boundary Scan (JTAG Port) timing diagram 72 bus address 2 data 2 multiplexed 2 non-multiplexed 2 bus acquisition timings 42 bus release timings 43, 44
C
clock external 4 operation 5 clocks internal 4
E
electrical design considerations 3 Enhanced Serial Audio Interface 4 ESAI 4, 2 ESSI receiver timing 66, 67 timings 62 transmitter timing 65 EXTAL jitter 5 external bus control 6, 7 external bus synchronous timings (SRAM access)
DSP56362 Technical Data, Rev. 4
D
data memory expansion 4 DAX 4, 2, 16 dc electrical characteristics 2 Debug support 3 design considerations
Freescale Semiconductor
Index-1
38 external clock operation 4 external interrupt timing (negative edge-triggered) 11 external level-sensitive fast interrupt timing 11 external memory access (DMA Source) timing 13 External Memory Expansion Port 14
I
instruction cache 3 internal clocks 4 interrupt and mode control 8 interrupt control 8 interrupt timing 7 external level-sensitive fast 11 external negative edge-triggered 11 synchronous from Wait state 12
F
functional groups 2 functional signal groups 1
J
Jitter 5 JTAG 20 JTAG Port 3 reset timing diagram 73 timing 70, 72
G
General Purpose Input/Output 4 GPIO 4, 2, 19 GPIO timing 69 Ground 4 PLL 4
M
maximum ratings 1 Memory Expansion Port 3 mode control 8 Mode select timing 7 multiplexed bus 2 multiplexed bus timings read 50 write 51
H
HDI08 4, 2, 10, 12, 13 DSP programming 6 DSP synchronization 6 Host synchronization 5 HDI08 timing 46 Host Interface 4, 2, 10, 12, 13 Host Interface timing 46 host port configuration 9 Host Port considerations 5 Host programming 5 Host Request Double 2 Single 2
N
non-multiplexed bus 2 non-multiplexed bus timings read 48 write 49
DSP56362 Technical Data, Rev. 4 Index-2 Freescale Semiconductor
O
off-chip memory 3 OnCE module timing 73 OnCE module 3, 20 Debug request 73 on-chip DRAM controller 4 On-Chip Emulation module 3 on-chip memory 3 operating mode select timing 12
S
Serial Host Interface 4, 14 SHI 4, 2, 14 signal groupings 1 signals 1 functional grouping 2 SRAM 40 Access 38 read access 17 read and write accesses 14 support 4 write access 17, 18 Stop mode 5 Stop state recovery from 12, 13 Stop timing 7 supply voltage 1 Switch mode 3 Synchronization 5 synchronous bus timings SRAM 2 wait states 41 SRAM 1 wait state (BCR controlled) 40 synchronous interrupt from Wait state timing 12 synchronous Reset timing 10
P
package 144-pin TQFP 1 TQFP description 1, 3 Phase Lock Loop 6 PLL 6 Characteristics 6 performance issues 4 PLL design considerations 4, 5 PLL performance issues 5 Port A 2 Port B 2, 10, 11, 12, 13 Port C 2, 16 Port D 2, 16 power consumption design considerations 3 power management 5 program memory expansion 4 program RAM 3
T
TAP 3 target applications 5 Test Access Port 3 Test Access Port timing diagram 72 Test Clock (TCLK) input timing diagram 71 thermal characteristics 2 thermal design considerations 1 Timer 4, 2, 19 event input restrictions 68 interrupt generation 68 timing 68 Timing Digital Audio Transmitter (DAX) 67
R
recovery from Stop state using IRQA 12, 13 RESET 9 Reset timing 7, 10 synchronous 10 ROM, bootstrap 3
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor Index-3
General Purpose I/O (GPIO) Timing 62 OnCETM (On Chip Emulator) Timing 62 Serial Host Interface (SHI) SPI Protocol Timing 52 Serial Host Interface (SHI) Timing 52 timing interrupt 7 mode select 7 Reset 7 Stop 7 TQFP 1 pin list by number 3 pin-out drawing (top) 1
W
Wait mode 5
X
X data RAM 3
Y
Y data RAM 3
DSP56362 Technical Data, Rev. 4 Index-4 Freescale Semiconductor
DSP56362 Technical Data, Rev. 4 Freescale Semiconductor Index-5
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Document Number: DSP56362 Rev. 4 08/2006

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